Start Cadence Innovus by typing /software/Cadence/INNOVUS211/tools/bin/innovus . Do not run in the background (by following the command with an "&"). If the terminal window shows "command not found", try again on a different ECE machine.
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Select File → Import Design from the menu bar.
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In the Netlist > Verilog > Files section, click …, click the open button in “Netlist Files” window, expand the window by clicking “>>”, add your netlist file (circ.vg) by double-clicking, and close the “Netlist Files” window.
Check “LEF Files” radio button, click …, expand the window by clicking “>>” , add the LEF file /software/classtools/EEC116/nangate_45_2011_v2010.12/NangateOpenCellLibrary_PDKv1_3_v2010_12/Back_End/lef/NangateOpenCellLibrary.lef by double clicking, and close the “LEF Files” window.
Library Exchange Format (LEF) gives the abstract information such as the PR boundary, pin positions and metal layers of a cell.
Enter Power > Power Nets: VDD
Ground Nets: VSS.Click OK.
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Before placing the standard cells, specify the design dimensions.
Select Floorplan → Specify Floorplane... from the menu bar.
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To distribute power around the chip, the core must be surrounded by power rings. To leave room for the power rings, set the core to IO boundary distance to 10 microns for all directions.
Set 10.0 for Core to Left, Core to Right, Core to Top and Core to Bottom.
Click OK.
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Place the power rings (VDD and VSS) within the core to IO boundary space that was made available in Section 2.
Click Power → Power Planning → Add Ring
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Enter Net(s): VDD VSS
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Use horizontal metal layers for top and bottom and use vertical metal layers for left and right to ensure metal rings run parallel to the core.
In Ring Configuration, select metal9(9)H in the pull-down menu next to Top and Bottom, and select metal8(8)V in the pull-down menu next to Left and Right.
Click OK.
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Place the vertical and horizontal power stripes so that power from the rings can reach the standard cells.
Click Power → Power Planning → Add Stripe
Enter Set Configuration > Net(s): VDD VSS
In Set Configuration > Layer, select metal4(4), and choose Width and Spacing using the values in the table below next to the last few digits from your SIS ID.
Enter Set Pattern > Set-to-set distance: 10
Click OK.
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Click Power → Connect Global Nets...
Click Connect > Pin radio button if not already selected.
Enter Pin Name(s): VDD
Enter To Global Net: VDD
Click: Add to List
Enter Pin Name(s): GND
Enter To Global Net: VSS
Click: Add to List
Click: Apply
Click: Cancel
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Select: Route → Special Route from the menu bar.
Enter Net(s): VDD VSS
Click OK.
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After power planning is finished, place the standard cells that you synthesized (circ.vg).
Select: Place → Place Standard Cell...
Click: Mode...
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Uncheck: Run Timing Driven Placement
Uncheck: Enable Clock Gating Awareness
Check: Place IO Pins
Click: OK.
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Click: OK to close the "Place" window.
You should see placed standard cells. If you do not, press "f" to refresh the display to zoom the chip to fill the window.
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Select: Route → NanoRoute → Route...
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Leave everything default and click OK to run routing.
Select: Verify → Verify Connectivity
Click: OK
Check the results displayed in the terminal window to verify there are "0 Viols" (violations) and "0 Wrngs" (warnings)
Click "z" to zoom into an area, "Z" to zoom out, and "f" to fill the screen.