University of California, Davis
Department of Electrical and Computer Engineering

EEC 180B – Digital Systems II
Spring 2006

Basic info

• Meets in 2107, Kemper Hall (Engineering II)
• Logging into computers in room 2107 requires that you have a standard ECE account name and password, which you should have if you are enrolled in the course. If you have not logged into an ECE HPUX or linux machine before, your username will be your UCD login name, and the password is as described in http://www.ece.ucdavis.edu/man/account/eceacct.htm.
  To make sure the first lab goes smoothly, try to log in to a lab machine during open lab hours before your first lab. If you have a problem, see someone in computer support in rooms 2156/2158/2160.
• In general, you are free to use the 2107 lab M-F 7am-7pm anytime a lab section is not using the room.
• The TA will normally close up the lab and ask students to leave at the end of the 4-hour lab period (esp. the night labs).
• No food or drinks are allowed in the lab. Note that equipment is connected to an alarm system so be careful to not move equipment which will set off the alarm.

Labs

• Lab 1: ModelSim/Synplicity/Xilinx Tutorial and Lab Exercise (week 2, 100 points)
• Lab 2: HIERARCHICAL DESIGN IN VHDL (week 3, 100 points)
• Lab 3: ALU Design (week 4, 100 points)
• Lab 4: Graphics Display Design (weeks 5&6: 200 points)
• Tutorial II (required for lab 4)
• Lab 5: µP1 Computer with Video Display (weeks 6&7&8: 300 points)
• Lab 6: Scan Testing (weeks 9&10: 100 points)

• You will pick up the laboratory descriptions from this page
• You will be working alone for all the labs. Cheating is strictly prohibited. Your work will be monitored closely and you will be prosecuted for submitting work that is NOT your OWN. 
• Pre-labs: 
• In order to ensure that you are prepared to do the laboratory exercise, we insist that you submit a short pre-lab report at the beginning of every lab exercise. Typically, for a VHDL laboratory exercise, the pre-lab report should include the detailed entity description (which captures the interface of your circuit) and the VHDL code of the architecture. You could also include a block-diagram or a state-diagram if necessary. The pre-lab report would constitute 10-25% of the lab grade. 
• Lab Report Should Contain:
• Pre-lab signed by the TA. 
• A brief description of your design, highlighting any special problems that you encountered, design decisions that you took, and the assumptions in your design. 
• A print-out of the VHDL code and simulation waveforms (double-sided). 
• Answers to the questions in the laboratory description handout, if any. 
• Verification sheet signed by the TA. (Download it from here: Lab report cover sheet)
• Lab reports are due in at the beginning of your lab section in the following week.
• Late completion/submission of reports will entail a 50% penalty per week of the TOTAL grade, i.e., 1 week late, 50% of total maximum credit; 2 weeks late, it’s yours.
  

• Spartan-3 Starter Kit Board User Guide (You can find pin assignments here.)
• Xilinx Home Page
• Spartan-3 FPGA Family: Complete Datasheet (All four modules)
• Spartan-3 FPGA Family: Introduction and Ordering Information
• Spartan-3 FPGA Family: Functional Description
• Spartan-3 FPGA Family: DC and Switching Characteristics
• Spartan-3 FPGA Family: Pinout Descriptions
• Xilinx Application Note: Using Block RAM in Spartan-3 Generation FPGA
• Synplicity Application Note: RAM Inferencing in Synplify Software Using Xilinx RAMS

Special thanks to Lance Halsted who developed and wrote up the labs.