A. Saxena, A. Bhattacharyya, L. Molina, S. Patil, and H. Al-Asaad, "Testing External Interrupts in the NEORV32 RISC-V Processor: Adapting ModelSim for Modern RISC-V Architecture", ICTIS 2025 (9th International Conference on ICT for Intelligent Systems), New York, May 23, 2025.

C. Tain, S. Patil, and H. Al-Asaad, "Survey of Verification of RISC-V Processors", Journal of Electronic Testing, 2025.

B. Tovar, C. Yee, R. Ng, H. Al-Asaad, and S. Patil, "Survey of RISC-V Pipelines and Testers", IEEE 15th Annual Computing and Communication Workshop and Conference (CCWC), 2025.

A. A. Zeraatkar, P. S. Kamran, I. Kaur, N. Ramu, T. Sheaves, and H. Al-Asaad, "On the Performance of Malware Detection Classifiers Using Hardware Performance Counters", International Conference on Smart Applications, Communications and Networking, 2024.

A. A. Zeraatkar, P. S. Kamran, and H. Al-Asaad, "Advancements in Secure Computing: Exploring Automated Repair Debugging and Verification Techniques for Hardware Design", IEEE 14th Annual Computing and Communication Workshop and Conference (CCWC), 2024.

R. Yarzada, D. Singh, and H. Al-Asaad, "A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays", IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC), 2022.

P. Sharma and H. Al-Asaad, "Brief Review of Low-Power GPU Techniques", Advances in Security, Networks, and Internet of Things: Proceedings from SAM, 2021.

S. Patil, S. Scholten, M. Tao, and H. Al-Asaad, "Survey of Memory, Timing, and Power Management Verification Methods for Multi-Core Processors", IEEE 10th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), 2019.

R. Sadre and H. Al-Asaad, "Machine Learning Applications in Digital System Verification", International Conference on Embedded Systems, Cyber-Physical Systems, and Applications, 2019.

A. Tobin and H. Al-Asaad, "Effectiveness of Intermediate Values at Outputs of Adder Designs", International Conference on Embedded Systems, Cyber-Physical Systems, and Applications, 2018.

Z. Ren and H. Al-Asaad, "Overview of Assertion-Based Verification and Its Applications", International Conference on Embedded Systems, Cyber-Physical Systems, and Applications, 2016.

M. Mahmoud, H. M. Elmaghraby, and H. Al-Asaad, "Design error injection, simulation, and diagnosis using FPGA-based boards", International Conference on Embedded Systems, Cyber-Physical Systems, and Applications, 2016, pp. 137–141.

Z. Zhao, H. Yan, and H. Al-Asaad, "Improving backup and recovery of modern data centers", International Conference on Advances in Big Data Analytics, 2015, pp. 43–49.

H. Al-Asaad and L. Bustamante, "Improving the Design and Reliability of Future Computer Systems via Using Intermediate Values of Outputs", IEEE AUTOTESTCON, 2015.

L. Bustamante and H. Al-Asaad, "Detection of Soft Errors Through Checksums in Redundant Execution Systems", IEEE AUTOTESTCON, 2015.

H. Al-Asaad, "Real-Time Scheduling of Multiple Executions of Tasks to Achieve Fault Tolerance in Multiprocessor Systems", IEEE AUTOTEST, 2014.

S. M. K. Kagadkar and H. Al-Asaad, "Allocation of NBTI Aging Sensors for Circuit Failure Prediction", International Conference on Computer Design (CDES), 2013.

L. Bustamante and H. Al-Asaad, "A Fault Injection Environment for the Evaluation of a Soft Error Detection Technique Based on Time Redundancy", International Conference on Computer Design (CDES), 2013.

L. Bustamante and H. Al-Asaad, "Soft Error Detection via Double Execution with Hardware Assistance", IEEE AUTOTESTCON, 2012.

A. Sayed and H. Al-Asaad, "Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design", International Journal of Engineering and Technology, 2011.

H. Al-Asaad, "Efficient Techniques for Reducing Error Latency in On-Line Periodic Built-In Self-Test", IEEE Instrumentation & Measurement Magazine, 2010.

J. Campos and H. Al-Asaad, "Automatically Generating an Input Sequence for a Circuit Design Using Mutant-Based Verification", US Patent 7,694,253, 2010.

H. Al-Asaad, "Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems", International Conference on Computer Design (CDES), 2010.

C. Chiem and H. Al-Asaad, "A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC–DC Converters", International Conference on Computer Design (CDES), 2010.

H. Al-Asaad, "New Global Fault Collapsing Techniques for Combinational Library Modules", International Journal of Modelling and Simulation, 2010.

H. Al-Asaad, "Efficient Techniques for Reducing Error Latency in On-Line Periodic BIST", IEEE AUTOTESTCON, pp. 173–177, 2009.

H. Al-Asaad, "Detection and isolation of faulty processors in multiprocessor systems via TMR-based time redundant task scheduling", International Conference on Computer Design (CDES), 2009, pp. 42–47.

C. Chiem and H. Al-Asaad, "Low power methodologies and challenges for PWM DC-DC converters", International Conference on Computer Design (CDES), 2009, pp. 70–75.

J. Campos and H. Al-Asaad, "A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16 (11), 2008.

A. S. Aldeen and H. Al-Asaad, "A New Method for Power Estimation and Optimization of Combinational Circuits", International Conference on Microelectronics, pp. 395–398, 2007.

A. Sayed and H. Al-Asaad, "A New Statistical Approach for Glitch Estimation in Combinational Circuits", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1641–1644, 2007.

H. Al-Asaad, "Efficient Global Fault Collapsing for Combinational Library Modules", Proc. International Conference on Computer Design (CDES), pp. 37–43, 2007.

J. Campos and H. Al-Asaad, "Circuit Profiling Mechanisms for High-Level ATPG", Seventh International Workshop on Microprocessor Test and Verification (MTV), 2006.

H. Al-Asaad and P. Moore, "Non-Concurrent On-Line Testing via Scan Chains", IEEE AUTOTESTCON, pp. 683–689, 2006.

A. Sayed and H. Al-Asaad, "A New Low Power High Performance Flip-Flop", IEEE Midwest Symposium on Circuits and Systems, 2006.

H. Al-Asaad, "AGFC: An Approximate Simulation-Based Global Fault Collapsing Tool for Combinational Circuits", Proc. International Conference on Circuits, Signals, and Systems, pp. 248–253, 2006.

H. Al-Asaad and P. Moore, "Non-concurrent on-line testing via scan chains", Autotestcon, 2006, pp. 683–689.

A. Sayed and H. Al-Asaad, "Survey and Evaluation of Low-Power Flip-Flops", Proc. International Conference on Computer Design (CDES), pp. 77–83, 2006.

J. Campos and H. Al-Asaad, "MVP: A Mutation-Based Validation Paradigm", Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.

J. Campos and H. Al-Asaad, "Search-Space Optimizations for High-Level ATPG", Sixth International Workshop on Microprocessor Test and Verification (MTV), pp. 84–89, 2005.

H. Al-Asaad, G. Valliappan, and L. Ramirez, "A Novel Functional Testing and Verification Technique for Logic Circuits", Proc. International Conference on Computer Design (CDES), pp. 129–135, 2005.

H. Al-Asaad, "EGFC: An Exact Global Fault Collapsing Tool for Combinational Circuits", Proc. Circuits, Signals, and Systems, pp. 56–61, 2005.

H. Arteaga and H. Al-Asaad, "On Increasing the Observability of Modern Microprocessors", International Conference on Computer Design (CDES), 2005, pp. 91–96.

J. Campos and H. Al-Asaad, "Mutation-Based Validation of High-Level Microprocessor Implementations", Ninth IEEE International High-Level Design Validation and Test Workshop, 2004.

J. Campos and H. Al-Asaad, "Concurrent Design Error Simulation for High-Level Microprocessor Implementations", IEEE AUTOTESTCON, pp. 382–388, 2004.

H. Arteaga and H. Al-Asaad, "Approaches for Monitoring Vectors on Microprocessor Buses", ESA/VLSI, pp. 393–398, 2004.

A. Sayed and H. Al-Asaad, "Survey and Evaluation of Low-Power Full-Adder Cells", ESA/VLSI, pp. 332–338, 2004.

H. Al-Asaad, "A Novel Markov Model for the Reliability Prediction of Fault Tolerant Non-Homogenous Multipipelines", IEEE AUTOTESTCON, 2003.

H. Al-Asaad and A. Sarvi, "Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling", VLSI, pp. 51–57, 2003.

H. Al-Asaad and R. Lee, "Simulation-Based Approximate Global Fault Collapsing", Proc. International Conference on VLSI, pp. 72–77, 2002.

H. Al-Asaad, "CAREER: A Comprehensive High-Level Design Validation Approach for Microprocessors", NSF Award No. 0092867, 2001.

H. Al-Asaad and J. P. Hayes, "Logic Design Validation via Simulation and Automatic Test Pattern Generation", Journal of Electronic Testing, vol. 16 (6), pp. 575–589, 2000.

H. Al-Asaad and M. Shringi, "On-Line Built-In Self-Test for Operational Faults", IEEE AUTOTESTCON, 2000.

H. Al-Asaad and J. P. Hayes, "ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits", IEEE VLSI Test Symposium, pp. 221–228, 2000.

H. Al-Asaad, J. P. Hayes, and T. Mudge, "Modeling and detecting control errors in microprocessors", Digest of Papers: International Congress on Dynamics & Control of Systems, 1999, pgs. 8.

H. Al-Asaad, B. T. Murray, and J. P. Hayes, "On-line BIST for embedded systems", IEEE Design and Test of Computers, Vol. 15, No. 4, pp. 17–24, November 1998.

D. Van Campenhout, H. Al-Asaad, J. P. Hayes, T. Mudge, and R. Brown, "High-level design verification of microprocessors via error modeling", ACM Transactions on Design Automation of Electronic Systems, Vol. 3, No. 4, pp. 581–599, October 1998.

H. Al-Asaad, "Lifetime Validation of Digital Systems via Fault Modeling and Test Generation", Ph.D. Dissertation, University of Michigan, Ann Arbor, September 1998.

H. Al-Asaad, J. P. Hayes, and B. T. Murray, "Scalable test generators for high-speed datapath circuits", Journal of Electronic Testing: Theory and Applications, Vol. 12, Nos. 1/2, pp. 111–125, February 1998.

H. Al-Asaad, D. Van Campenhout, J. P. Hayes, T. Mudge, and R. Brown, "High-level design verification of microprocessors via error modeling", Digest of Papers: International High-Level Design Validation & Test Workshop, 1997, pp. 194–201.

H. Al-Asaad, J. P. Hayes, and B. T. Murray, "Design of scalable hardware test generators for online BIST", Digest of Papers: International On-Line Testing Workshop, 1996, pp. 164–167.

H. Al-Asaad and J. P. Hayes, "Design verification via simulation and automatic test pattern generation", International Conference on Computer-Aided Design, 1995, pp. 174–180.

H. Al-Asaad, M. Vai, and J. Feldman, "Distributed Reconfiguration of Fault Tolerant VLSI Multipipeline Arrays with Constant Interstage Path Lengths", IEEE International Conference on Computer Design, 1994.

H. Al-Asaad, "On the Design of Fault-Tolerant VLSI and WSI Non-Homogenous Multipipelines", M.S. Thesis, Northeastern University, Boston, September 1993.

H. Al-Asaad and E. S. Manolakos, "A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays out of Two-Dimensional Architectures", IEEE International Workshop on Defect and Fault Tolerance, 1993.

H. Al-Asaad and E. Czeck, "Concurrent Error Correction in Iterative Circuits by Recomputing with Partitioning and Voting", IEEE VLSI Test Symposium, pp. 174–177, 1993.

H. Al-Asaad and M. Vai, "A Real-Time Reconfiguration Algorithm for Fault-Tolerant VLSI and WSI Arrays", IEEE International Workshop on Defect and Fault Tolerance, 1992.