Project
Current Projects
RISC-V Verification Automation Framework
Members: Pavan Dheeraj Kota, Kilho Chang, and Savita Patil
FPGA-Emulated Framework for RTL Verification of RISC-V Processors
(FERIVer-Inspired Replication & Extension)
Members: Pranjal Trivedi, YaTing Chang, Kanvar Austin Sidhu, Bo Lu, Anthony Yan, and Savita PatilTesting Digital Systems Using Machine Learning – A Comparative Study
Members: Jasem Ali, Lisa Verma, Tsenbujin Tsendjav, Manya Bhuvan Murali, and Savita Patil
Functional Verification and Fault Modeling of a RISC-V Register File
Members: Camille Chang and Savita Patil
Enhancing RISC-V Verification and Coverage Using Imperas DV and Synopsys Tools
Members: Open to graduate and undergraduate students with Savita Patil
Deploying and Accelerating Object Detection Models on Resource-Constrained Devices
Members: Arunima Saxena