See Prof. Aaron Stillmaker's website for up to date information, this site will no longer be updated.


University of California, Davis, CA
Ph.D., Electrical and Computer Engineering, 2015
Major: Digital Design and Computer Systems; Minor:Signals and Systems
Dissertation: "Design of Energy-Efficient Many-Core MIMD GALS Processor Arrays in the 1000-Processor Era"
Advisor: Dr. Bevan Baas

University of California, Davis, CA
M.S., Electrical and Computer Engineering, 2013

California State University, Fresno, CA
B.S., Magna Cum Laude, Smittcamp Honors Scholar, 2008
Major: Computer Engineering; Minor:Bussiness



UC Davis:

Associate Instructor:

Teaching Assistant:
Fresno State:
Teaching Assistant:


Test of 3rd generation VCL many-core processor array.

Development of area-efficient SAR ASIC.
Asilomar 2015

Physical design of 4rd generation VCL many-core processor array.

Physical design of 3rd generation VCL many-core processor array.

Designing parallel database sorting algorithms for the AsAP2 chip.
UCD Industrial Affiliates 2011

Characterizing the scaling of power and delay as technology sizes scale, so as to make better comparisons to circuitry in different techology sizes.
Technical Report

Researching enterprise workloads suitable for a fine-grained many-core processor array

Dual clock FIFO in Verilog for communication between two different clock frequencies.
Dual Clock FIFO

Professional Services

  • Reviewer for IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
  • Reviewer for IEEE Journal of Solid-State Circuits (JSSC)
  • Reviewer for IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
  • Reviewer for IEEE Design and Test of Computers
  • Reviewer for IEEE Micro
  • Reviewer for IEEE International Conference on Computer Design (ICCD)
  • Chapter Advisor for CA-L Tau Beta Pi Chapter at UC Davis

This page was last modified on 3/29/2016.