4 units – Fall Quarter
Lecture: 3 hours
Laboratory: 3 hours
Prerequisites: EEC 110A
CMOS devices, layout, circuits, and functional units; VLSI fabrication and design methodologies.
Expanded Course Description:
Computer Usage and Laboratory Projects:
Students will use Magic or Candence layout tools on several homework projects. These projects will include substantial design at various levels including chip level, functional unit, circuit, and physical layout.
Engineering Design Statement:
Students will be required to work in groups on a project consisting of the full-custom layout of a VLSI block including circuit and logic design. The design must meet functional and minimum performance requirements and will be judged by its performance, area, and power dissipation.
Relationship to Outcomes:
Students who have successfully completed this course should have achieved:
|Course Outcomes||ABET outcomes|
|An ability to apply knowledge of mathematics, science, and engineering||A|
|An ability to identify, formulate, and solve engineering problems||E|
Engineering Depth, Laboratory, Project
Engineering Science: 2 credits
Engineering Design: 2 credits
There is a small amount of overlap with EEC 118 (about 10%), but this course has an entirely different focus. EEC 118 deals with detailed transistor-level digital circuits while this course focuses on very large scale integrated circuit (VLSI) design issues.