UNIVERSITY OF CALIFORNIA, DAVIS

Department of Electrical and Computer Engineering

EEC180B

Digital Systems II

Instructor: (April 2 - April 26)

Professor Vojin G. Oklobdzija

Office: Engineering II, Room 3007

(Prof. Oklobdzija is on medical leave as of April 28)

Instructor: (April 28 - end of quarter)

Lance Halsted

Office: Engineering II, Room 2123

Office Hours: Tuesday, Friday 2-4pm or by appointment

Email: halsted@ece.ucdavis.edu

Teaching Assistants

Mutlu Koca / koca@ece.ucdavis.edu

George Terziev / terziev@ece.ucdavis.edu

Index:

• Course Information
• Reading Assignments
• Homework
• Labs
• Reference Material, Lecture Slides, Errata
• Downloading Acrobat Reader

Announcements

• Prof. Oklobdzija is on medical leave as of April 28. Lance Halsted will be teaching the course in his absence. There will be some significant changes in the course material and a new required text.
• Quiz Schedule:
  • Wed. 5/19 - on Ch. 2, Labs 4 & 5;
    Location: 198 Young; Format: CLOSED NOTES, CLOSED BOOK
  • Wed. 5/26 - on Ch. 4 & 5; Labs 5 & 6;
    Lcation: 194 Young; Format: CLOSED NOTES, CLOSED BOOK
  • Mon. 6/7 - on delta delays, inertial & transport delays, drivers and resolution functions;
    Lcation: 194 Young; Format: CLOSED NOTES, CLOSED BOOK


• FINAL EXAM: Monday, June 14, 8:00-10:00am,
  Location: 198 Young; Format: OPEN NOTES, OPEN BOOK
• If you need to find out your final exam score and/or course grade, send me an email and I will email your information to you.

Course Information

• Original Course Outline
• Orignal Reading Assignments
• Revised Course Outline (4/28 to end of quarter)
• Homework and Lab Policies
• Revised Grading Policy
(5/12)

Reading Assignments

• 4/28 Roth VHDL text: skim Ch. 1; read 1.10-1.12; read Ch 2;
• 5/3 Roth VHDL text: Ch. 8.8-8.9;
  Synopsys on-line document: Ch. 3 of Guidelines & Practices for Logic Synthesis (use SOLD - look under Synthesis Tools Collection : Printing)
• 5/10 Roth VHDL text: Ch. 4-4.3;
• 5/12 Roth VHDL text: Ch. 4.5 (p. 144-148); Ch. 5 (skip 5.5);
• 5/24 Roth VHDL text: Ch. 8.1-8.7;
• 5/26 Roth VHDL text: Ch. 6, focusing on 6.4 and basic FPGA architectures;
  Xilinx on-line document: Ch. 5 of Synopsys (XSI) Interface manual for reference information on gate-level simulation and using STARTBUF to reset all Xilinx flip-flops. (available via dtext)

Homework

• Homework 1, FIFO redesign & Register File
• Homework 2, Problems from Ch. 2
• Homework 3, Problems from Ch. 4 and 5
• Homework 4, Problems from Ch. 6 and 8

Labs

• Lab Report Cover Sheet
• Lab 1, Powerview Tutorial
• Lab 1, Figure 1
• Lab 1, Figure 2
• Lab 1, Figure 3
• Lab 1, Figure 4
• Lab 1, Figure 5
• Lab 1, Figure 6
• Lab 2, Xilinx Tutorial
• Lab 2, Figure 1
• Lab 2, Figure 2
• Lab 2, Figure 3
• Lab 3, Synopsys/Xilinx Tutorial
• Lab 4, Structural Modeling in VHDL
• Lab 5, State Machine Design in VHDL
• Lab 6, Register File Design in VHDL
• Lab 7, Processor Design in VHDL
• Pipelined Processor Datapath
• Pipelined Processor Lab

Reference Material, Lecture Slides, Errata

• VHDL code examples from text
• Errata list and lecture slides from text
• 5/3 lecture slides (text slides not included)
• 5/10 binary multiplier - VHDL code
• 5/10 binary multiplier - test bench code
• 5/17 lecture slides
• 5/17 lecture slide - simulation cycle

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Downloading Acrobat Reader

To access any file in the sections with the icon, you will need to use the Acrobat Reader. If you do not have a copy of the Reader, you can download it from Adobe:

Steps to Downloading the free Adobe Acrobat Reader

(Page last modified: Thursday, 07-Oct-1999 13:33:43 PDT)