EEC180B                                  DIGITAL SYSTEMS II                                   Spring 1999

COURSE OUTLINE

Instructor: Professor Vojin G. Oklobdzija ( Voi-n O-klob-j-i-a)

Office: 3007 EU-II, Phone: 752-5634
Office Hours: M-W 6:30-7:30 by appointment and via e-mail.

E-mail: vojin@ece.ucdavis.edu

Course Grading:
Þ Midterm:                 May 5, 1999             25%
FINAL EXAM                                                 40%
HOMEWORKS                                                5%
QUIZES &                                                        15%
LABORATORY                                              15%
  Scheduling: Holidays:  
  Course Text:
 
  1. Charles J. Roth, Fundamentals of Logic Design, West Publishing Co., 1993.
  2. D. Patterson, J. Hennessy, "Computer Organization and Design: The Hardware/Software Interface".
  3. V. G. Oklobdzija, "Digital Design", set of papers, available at Navin's.
    4.  
     
Additional References: (Physical Sciences Library):
 
  1. L.H. Polard The Design Book: Techniques and Solutions for Digital Computer Systems, Prentice Hall 1990.
  2. M.Ercegovac, T.Lang Digital Systems and Hardware /Firmware Algorithms, John Wiley & Sons, 1985
  3. V. Nelson Digital Logic Circuit Analysis and Design, Prentice-Hall, 1995.
  4. D. J. Comer Digital Logic and State Machine Design, Sounders College Publishing, 1995.
  5. Mano, M. M. Digital Design (Second Edition), Prentice-Hall, 1991.
  6. Texas Instruments, Inc. The TTL Data Book for Design Engineers (Second Edition), 1981.

ORDERED TOPICS AND PERTINENT TEXT SECTIONS

Charles H. Roth, Fundamentals of Logic Design, West Publishing Company
*D. Patterson, J. Hennessy, "Computer Organization and Design: The Hardware/Software Interface", Morgan Kaufmann Publishers.
Topics
Text Sections
Review Material (required EEC180A knowledge):  
Karnaugh Maps  6.1 - 6.4, 6.6-6.7
Multi-Level Gate Networks  8.1 - 8.7
Multiplexers, Decoders, ROM and PLA  9.1 - 9.7
Combinational Network Design  10.1 – 10.3
Flip-Flops  11.1 – 11.9
Counters and Sequential Networks  12.1 - 12.9
Analysis of Clocked Sequential Networks  13.1 - 13.4
Derivation of State Graphs and Tables  14.1-14.4
Reduction of State Tables, State Assignment  15.1-15.8
Sequential Network Design  16.1 - 16.4
Discrete and Integrated Circuit Logic Gates  A.1 - A.4
EEC180B Material  
Iterative Networks  17.1 - 17.4
Networks for Addition and Subtraction  20.1 - 20.3
Instructions: Language of the Machine  3.1 - 3.6*
Arithmetic for Computers*  4.1 - 4.12*
MSI Integrated Circuits in Sequential Network Design  18.1 - 18.4
Sequential Network Design with PLDs  19.1 - 19.4
State Machine Design with SM Charts  22.1 - 22.3
Analysis of Asynchronous Sequential Networks  23.1 - 23.4
Derivation and Reduction of Primitive Flow Tables  24.1 - 24.2
State Assignment and Realization of Flow Tables  25.1 - 25.5
The Processor: Datapath and Control*  5.1 - 5.10*
Enhancing Performance with Pipelining*  6.1 - 6.5*
Hazards  26.1 - 26.4
Mapping Control to Hardware*  C.1 - C.6*