Sasan professor & laboratory responsive template

[c71] Ali Mirzaeian, Jana Kosecka, Houman Homayoun, Tinoosh Mohsenin, Avesta Sasan,

Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks, ISQED, 2021, pp. 1-6. PDF

DOI: 10.xxxx/ISQEDxxxxx.2020.xxxxxxx

[c70] Ali Mirzaeian, Sai Manoj PD, Ashkan Vakil, Houman Homayoun, Avesta Sasan,

Conditional Classification: A Solution for Computational Energy Reduction, ISQED, 2021, pp. 1-6. PDF

DOI: 10.xxxx/ISQEDxxxxx.2020.xxxxxxx

[c69] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan,

ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing, ISQED, 2021, pp. 1-7. PDF

DOI: 10.xxxx/ISQEDxxxxx.2020.xxxxxxx

[c68] Ashkan Vakil, Farzad Niknia, Ali Mirzaeian, Avesta Sasan, Naghmeh Karimi,

Learning Assisted Side Channel Delay Test for Detection of Recycled ICs, ASP-DAC, 2021, pp. 455-462. PDF

DOI: 10.1145/3394885.3431640

[c67] Hadi Mardani Kamali, Kimia Zamiri Azar, Shervin Roshanisefat, Ashkan Vakil, Avesta Sasan,

Extru: A lightweight, fast, and secure expirable trust for the internet of things, DCAS, 2020, pp. 1-6. PDF

DOI: 10.1109/DCAS51144.2020.9330632

[c65] Ali Mirzaeian, Houman Homayoun, Avesta Sasan,

NESTA: Hamming Weight Compression-Based Neural Proc. Engine, ASP-DAC, 2020, pp. 530-537. PDF

DOI: 10.1109/ASP-DAC47756.2020.9045135

[c64] Han Wang, Hossein Sayadi, Tinoosh Mohsenin, Liang Zhao, Avesta Sasan, Setareh Rafatirad, Houman Homayoun,

Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis, DATE, 2020, pp. 1414-1419. PDF

DOI: 10.23919/DATE48585.2020.9116340

[c63] Aidin Shiri, Arnab Neelim Mazumder, Bharat Prakash, Nitheesh Kumar Manjunath, Houman Homayoun, Avesta Sasan, Nicholas R. Waytowich, Tinoosh Mohsenin,

Energy-Efficient Hardware for Language Guided Reinforcement Learning, GLSVLSI, 2020, pp. 131-136. PDF

DOI: 10.1145/3386263.3407652

[c62] Hossein Sayadi, Yifeng Gao, Hosein Mohammadi Makrani, Tinoosh Mohsenin, Avesta Sasan, Setareh Rafatirad, Jessica Lin, Houman Homayoun,

StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features, GLSVLSI, 2020, pp. 175-180. PDF

DOI: 10.1145/3386263.3407585

[c61] Han Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Tinoosh Mohsenin, Houman Homayoun,

Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks, GLSVLSI, 2020, pp. 181-186. PDF

DOI: 10.1145/3386263.3407586

[c60] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan,

On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic, GLSVLSI, 2020, pp. 217-222. PDF

DOI: 10.1145/3386263.3407655

[c59] Han Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Houman Homayoun,

Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks, ICCAD, 2020, pp. 36:1-36:9. PDF

DOI: 10.1145/3400302.3418783

[c58] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan,

InterLock: An Intercorrelated Logic and Routing Locking, ICCAD, 2020, pp. 78:1-78:9. PDF

DOI: 10.1145/3400302.3415667

[c57] Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan,

NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures, ICCAD, 2020, pp. 79:1-79:9. PDF

DOI: 10.1145/3400302.3415669

[c56] Han Wang, Hossein Sayadi, Gaurav Kolhe, Avesta Sasan, Setareh Rafatirad, Houman Homayoun,

Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks, ICCD, 2020, pp. 648-655. PDF

DOI: doi.org/10.1109/ICCD50377.2020.00111

[c55] Han Wang, Hossein Sayadi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun,

SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features, IOLTS, 2020, pp. 1-6 . PDF

DOI: 10.1109/IOLTS50870.2020.9159708

[c54] Farnaz Behnia, Ali Mirzaeian, Mohammad Sabokrou, Sai Manoj P. D., Tinoosh Mohsenin, Khaled N. Khasawneh, Liang Zhao, Houman Homayoun, Avesta Sasan,

Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks, ISQED, 2020, pp. 27-32 . PDF

DOI: 10.1109/ISQED48828.2020.9136987

[c53] Ashkan Vakil, Farnaz Behnia, Ali Mirzaeian, Houman Homayoun, Naghmeh Karimi, Avesta Sasan,

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection, ISQED, 2020, pp. 40-45 . PDF

DOI: 10.1109/ISQED48828.2020.9137007

[c52] Hirenkumar Paneliya, Morteza Hosseini, Avesta Sasan, Houman Homayoun, Tinoosh Mohsenin,

CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator, ISQED, 2020, pp. 311-316 . PDF

DOI: 10.1109/ISQED48828.2020.9137013

[c51] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan,

SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption, ISVLSI, 2020, pp. 153-159 . PDF

DOI: 10.1109/ISVLSI49217.2020.00037

[c50] Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan,

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain, VTS, 2020, pp. 1-6 . PDF

DOI: 10.1109/VTS48691.2020.9107629

[c49] Ashkan Vakil, Houman Homayoun, Avesta Sasan

IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure, ASP-DAC, 2019, pp. 152-159. PDF

DOI: 10.1145/3287624.3287683

[c48] Hosein Mohammadi Makrani, Hossein Sayadi, Tinoosh Mohsenin, Setareh Rafatirad, Avesta Sasan, Houman Homayoun,

XPPE: cross-platform performance estimation of hardware accelerators using machine learning, ASP-DAC, 2019, pp. 727-732. PDF

DOI: 10.1145/3287624.3288756

[c47] Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao, Avesta Sasan, Houman Homayoun, Setareh Rafatirad,

Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design, FPL, 2019, pp. 397-403. PDF

DOI: 10.1109/FPL.2019.00069

[c46] Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks, DAC, 2019, pp. 89:1-6. PDF

DOI: 10.1145/3316781.3317831

[c45] Sai Manoj Pudukotai Dinakarrao, Sairaj Amberkar, Sahil Bhat, Abhijitt Dhavlle, Hossein Sayadi, Avesta Sasan, Houman Homayoun, Setareh Rafatirad

Adversarial Attack on Microarchitectural Events based Malware Detectors, DAC, 2019, pp. 164:1-6. PDF

DOI: 10.1145/3316781.3317762

[c44] Hossein Sayadi, Hosein Mohammadi Makrani, Sai Manoj Pudukotai Dinakarrao, Tinoosh Mohsenin, Avesta Sasan, Setareh Rafatirad, Houman Homayoun

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection, DATE, 2019, pp. 728-733. PDF

DOI: 10.23919/DATE.2019.8715080

[c43] Mahmoud Namazi, Hosein Mohammadi Makrani, Zhi Tian, Setareh Rafatirad, Mohamad Hosein Akbari, Avesta Sasan, Houman Homayoun

Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching, GLSVLSI, 2019, pp. 219-224. PDF

DOI: 10.1145/3299874.3317991

[c42] Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

Threats on Logic Locking: A Decade Later, GLSVLSI, 2019, pp. 471-476. PDF

DOI: 10.1145/3299874.3319495

[c41] Gaurav Kolhe, Sai Manoj P. D., Setareh Rafatirad, Hamid Mahmoodi, Avesta Sasan, Houman Homayoun

On Custom LUT-based Obfuscation, GLSVLSI, 2019, pp. 477-482. PDF

DOI: 10.1145/3299874.3319496

[c40] Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi, Sai Manoj P. D., Houman Homayoun, Setareh Rafatirad, Avesta Sasan

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality, ICCAD, 2019, pp. 1-8. PDF

DOI: 10.1109/ICCAD45719.2019.8942100

[c39] Maria Malik, Hassan Ghasemzadeh, Tinoosh Mohsenin, Rosario Cammarota, Liang Zhao, Avesta Sasan, Houman Homayoun, Setareh Rafatirad

ECoST: Energy-Efficient Co-Locating and Self-Tuning MapReduce Applications, ICPP, 2019, pp. 1-11. PDF

DOI: 10.1145/3337821.3337834

[c38] Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan

Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks, ISQED, 2019, pp. 265-270. PDF

DOI: 10.1109/ISQED.2019.8697497

[c37] Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan

COMA: Communication and Obfuscation Management Architecture, ISQED, 2019, pp. 265-270. PDF

DOI: 10.xxxx

[c36] Ali Mirzaeian, Houman Homayoun, Avesta Sasan

TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs, ReConFig, 2019, pp. 1-8. PDF

DOI: 10.1109/ReConFig48160.2019.8994751

[c35] Ferdinand Brasser, Lucas Davi, Abhijitt Dhavlle, Tommaso Frassetto, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad, Ahmad-Reza Sadeghi, Avesta Sasan, Hossein Sayadi, Shaza Zeitouni, Houman Homayoun,

Advances and throwbacks in hardware-assisted security: special session, CASES, 2018, pp. 1-10. PDF

DOI: 10.1109/CASES.2018.8516874

[c34] Hossein Sayadi, Nisarg Patel, Sai Manoj P. D., Avesta Sasan, Setareh Rafatirad, Houman Homayoun,

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification, DAC, 2018, pp. 1-6. PDF

DOI: 10.1109/DAC.2018.8465828

[c33] Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan,

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation, DATE, 2018, pp. 551-556. PDF

DOI: 10.23919/DATE.2018.8342068

[c32] Katayoun Neshatpour, Hosein Mohammadi Makrani, Avesta Sasan, Hassan Ghasemzadeh, Setareh Rafatirad, Houman Homayoun,

Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce, FCCM, 2018, pp. 221:1-8. PDF

DOI: 10.1109/FCCM.2018.00055

[c31] Shervin Roshanisefat, Hadi Mardani Kamali, Avesta Sasan,

SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware, GLSVLSI, 2018, pp. 153-158. PDF

DOI: 10.1145/3194554.3194596

[c30] Hadi Mardani Kamali, Avesta Sasan,

MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture, GLSVLSI, 2018, pp. 459-462. PDF

DOI: 10.1145/3194554.3194648

[c29] Hadi Mardani Kamali, Avesta Sasan,

Low Power and Trusted Machine Learning, GLSVLSI, 2018, pp. 515. PDF

DOI: 10.1145/3194554.3216321

[c28] Shervin Roshanisefat, Harshith K. Thirumala, Kris Gaj, Houman Homayoun, Avesta Sasan,

Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes, IOLTS, 2018, pp. 275-280. PDF

DOI: 10.1109/IOLTS.2018.8474189

[c27] Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan,

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection, ISVLSI, 2018, pp. 405-410. PDF

DOI: 10.1109/ISVLSI.2018.00080

[c26] Katayoun Neshatpour, Hosein Mohammadi Makrani, Avesta Sasan, Hassan Ghasemzadeh, Setareh Rafatirad, Houman Homayoun,

Architectural considerations for FPGA acceleration of machine learning applications in MapReduce, SAMOS, 2018, pp. 89-96. PDF

DOI: 10.1145/3229631.3229639

[c25] Nisarg Patel, Avesta Sasan, Houman Homayoun,

Analyzing Hardware Based Malware Detectors, DAC, 2017, pp. 25:1-25:6. PDF

DOI: 10.1145/3061639.3062202

[c24] Maria Malik, Katayoun Neshatpour, Tinoosh Mohsenin, Avesta Sasan, Houman Homayoun,

Big vs little core for energy-efficient Hadoop computing, DATE, 2017, pp. 1480-1485. PDF

DOI: 10.23919/DATE.2017.7927225

[c23] Hossein Sayadi, Nisarg Patel, Avesta Sasan, Houman Homayoun,

Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures, ICCD, 2017, pp. 129-135. PDF

DOI: 10.1109/ICCD.2017.28

[c22] Bhoopal Gunna, Lakshmi Bhamidipati, Houman Homayoun, Avesta Sasan,

Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction, ISLPED, 2017, pp. 1-6. PDF

DOI: 10.1109/ISLPED.2017.8009179

[c21] Lakshmi Bhamidipati, Bhoopal Gunna, Houman Homayoun, Avesta Sasan,

A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews, ISLPED, 2017, pp. 272-277. PDF

DOI: 10.1109/ISVLSI.2017.55

[c20] Katayoun Neshatpour, Avesta Sasan, Houman Homayoun,

Big data analytics on heterogeneous accelerator architectures, CODES-ISSS, 2016, pp. 1-16. PDF

DOI: 10.1145/2968456.2976765

[c19] Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv V. Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun,

Big biomedical image processing hardware acceleration: A case study for K-means and image filtering, ISCAS, 2016, pp. 1134-1137. PDF

DOI: 10.1109/ISCAS.2016.7527445

[c18] Maria Malik, Avesta Sasan, Rajiv V. Joshi, Setareh Rafatirah, Houman Homayoun,

Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations, ISPASS, 2016, pp. 153-154. PDF

DOI: 10.1109/ISPASS.2016.7482087

[c17] Maria Malik, Setareh Rafatirah, Avesta Sasan, Houman Homayoun,

System and architecture level characterization of big data applications on big and little core server architectures, BigData, 2015, pp. 85-94. PDF

DOI: 10.1109/BigData.2015.7363745

[c16] Katayoun Neshatpour, Maria Malik, Mohammad Ali Ghodrat, Avesta Sasan, Houman Homayoun,

Energy-efficient acceleration of big data analytics applications using FPGAs, BigData, 2015, pp. 115-123. PDF

DOI: doi.org/10.1109/BigData.2015.7363748

[c15] Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi,

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring, ISQED, 2012, pp. 498-505. PDF

DOI: 10.1109/ISQED.2012.6187540

[c14] Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt,

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units, Frontiers, 2010, pp. 297-308. PDF

DOI: 10.1145/1787275.1787339

[c13] Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil D. Dutt,

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor, HiPEAC, 2010, pp. 216-231. PDF

DOI: 10.1007/978-3-642-11515-8_17

[c12] Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi,

A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache), CASES, 2009, pp. 251-260. PDF

DOI: 10.1145/1629395.1629431

[c11] Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi,

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling, DATE, 2009, pp. 911-916. PDF

DOI: 10.1109/DATE.2009.5090795

[c10] Mani Zarei, Amir Masoud Rahmani, Avesta Sasan, Mohammad Teshnehlab,

Fuzzy Based Trust Estimation for Congestion Control in Wireless Sensor Networks, INCoS, 2009, pp. 233-236. PDF

DOI: 10.1109/INCOS.2009.16

[c9] Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum,

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors, CASES, 2008, pp. 197-206. PDF

DOI: 10.1145/1450095.1450125

[c8] Houman Homayoun, Sudeep Pasricha, Avesta Sasan, Alexander V. Veidenbaum,

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency, DAC, 2008, pp. 68-71. PDF

DOI: 10.1145/1391469.1391488

[c7] Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum,

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits, ICCD, 2008, pp. 699-706. PDF

DOI: 10.1109/ICCD.2008.4751937

[c6] Houman Homayoun, Sudeep Pasricha, Avesta Sasan, Alexander V. Veidenbaum,

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors, LCTES, 2008, pp. 71-78. PDF

DOI: 10.1109/ICCD.2008.4751937

[c5] Houman Homayoun, Sudeep Pasricha, Avesta Sasan, Alexander V. Veidenbaum,

Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices, ICSAMOS, 2008, pp. 124-131. PDF

DOI: 10.1109/ICSAMOS.2008.4664855

[c4] Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum,

A centralized cache miss driven technique to improve processor power dissipation, ICSAMOS, 2008, pp. 124-131. PDF

DOI: 10.1109/ICSAMOS.2008.4664864

[c3] Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Avesta Sasan, Stanley Cheng,

Error-Aware Design, DSD, 2007, pp. 8-15. PDF

DOI: 10.1109/DSD.2007.4341443

[c2] Avesta Sasan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi,

Limits on voltage scaling for caches utilizing fault tolerant techniques, ICCD, 2007, pp. 488-495. PDF

DOI: 10.1109/ICCD.2007.4601943

[c1] Avesta Sasan, Kwei-Jay Lin

Solutions to a Complete Web Service Discovery and Composition, CEC/EEE, 2006, pp. 73. PDF

DOI: 10.1109/CEC-EEE.2006.83

Publication

Conference Papers