Conference Papers

Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks, ISQED, 2021, pp. 1-6. PDF

Conditional Classification: A Solution for Computational Energy Reduction, ISQED, 2021, pp. 1-6. PDF

ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing, ISQED, 2021, pp. 1-7. PDF

Learning Assisted Side Channel Delay Test for Detection of Recycled ICs, ASP-DAC, 2021, pp. 455-462. PDF

Extru: A lightweight, fast, and secure expirable trust for the internet of things, DCAS, 2020, pp. 1-6. PDF

NESTA: Hamming Weight Compression-Based Neural Proc. Engine, ASP-DAC, 2020, pp. 530-537. PDF

Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis, DATE, 2020, pp. 1414-1419. PDF

Energy-Efficient Hardware for Language Guided Reinforcement Learning, GLSVLSI, 2020, pp. 131-136. PDF

StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features, GLSVLSI, 2020, pp. 175-180. PDF

Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks, GLSVLSI, 2020, pp. 181-186. PDF

On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic, GLSVLSI, 2020, pp. 217-222. PDF

Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks, ICCAD, 2020, pp. 36:1-36:9. PDF

InterLock: An Intercorrelated Logic and Routing Locking, ICCAD, 2020, pp. 78:1-78:9. PDF

NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures, ICCAD, 2020, pp. 79:1-79:9. PDF

Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks, ICCD, 2020, pp. 648-655. PDF

SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features, IOLTS, 2020, pp. 1-6 . PDF

Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks, ISQED, 2020, pp. 27-32 . PDF

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection, ISQED, 2020, pp. 40-45 . PDF

CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator, ISQED, 2020, pp. 311-316 . PDF

SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption, ISVLSI, 2020, pp. 153-159 . PDF

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain, VTS, 2020, pp. 1-6 . PDF

IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure, ASP-DAC, 2019, pp. 152-159. PDF

XPPE: cross-platform performance estimation of hardware accelerators using machine learning, ASP-DAC, 2019, pp. 727-732. PDF

Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design, FPL, 2019, pp. 397-403. PDF

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks, DAC, 2019, pp. 89:1-6. PDF

Adversarial Attack on Microarchitectural Events based Malware Detectors, DAC, 2019, pp. 164:1-6. PDF

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection, DATE, 2019, pp. 728-733. PDF

Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching, GLSVLSI, 2019, pp. 219-224. PDF

Threats on Logic Locking: A Decade Later, GLSVLSI, 2019, pp. 471-476. PDF

On Custom LUT-based Obfuscation, GLSVLSI, 2019, pp. 477-482. PDF

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality, ICCAD, 2019, pp. 1-8. PDF

ECoST: Energy-Efficient Co-Locating and Self-Tuning MapReduce Applications, ICPP, 2019, pp. 1-11. PDF

Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks, ISQED, 2019, pp. 265-270. PDF

COMA: Communication and Obfuscation Management Architecture, ISQED, 2019, pp. 265-270. PDF

DOI: 10.xxxx

TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs, ReConFig, 2019, pp. 1-8. PDF

Advances and throwbacks in hardware-assisted security: special session, CASES, 2018, pp. 1-10. PDF

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification, DAC, 2018, pp. 1-6. PDF

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation, DATE, 2018, pp. 551-556. PDF

Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce, FCCM, 2018, pp. 221:1-8. PDF

SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware, GLSVLSI, 2018, pp. 153-158. PDF

MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture, GLSVLSI, 2018, pp. 459-462. PDF

Low Power and Trusted Machine Learning, GLSVLSI, 2018, pp. 515. PDF

Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes, IOLTS, 2018, pp. 275-280. PDF

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection, ISVLSI, 2018, pp. 405-410. PDF

Architectural considerations for FPGA acceleration of machine learning applications in MapReduce, SAMOS, 2018, pp. 89-96. PDF

Analyzing Hardware Based Malware Detectors, DAC, 2017, pp. 25:1-25:6. PDF

Big vs little core for energy-efficient Hadoop computing, DATE, 2017, pp. 1480-1485. PDF

Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures, ICCD, 2017, pp. 129-135. PDF

Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction, ISLPED, 2017, pp. 1-6. PDF

A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews, ISLPED, 2017, pp. 272-277. PDF

Big data analytics on heterogeneous accelerator architectures, CODES-ISSS, 2016, pp. 1-16. PDF

Big biomedical image processing hardware acceleration: A case study for K-means and image filtering, ISCAS, 2016, pp. 1134-1137. PDF

Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations, ISPASS, 2016, pp. 153-154. PDF

System and architecture level characterization of big data applications on big and little core server architectures, BigData, 2015, pp. 85-94. PDF

Energy-efficient acceleration of big data analytics applications using FPGAs, BigData, 2015, pp. 115-123. PDF

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring, ISQED, 2012, pp. 498-505. PDF

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units, Frontiers, 2010, pp. 297-308. PDF

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor, HiPEAC, 2010, pp. 216-231. PDF

A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache), CASES, 2009, pp. 251-260. PDF

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling, DATE, 2009, pp. 911-916. PDF

Fuzzy Based Trust Estimation for Congestion Control in Wireless Sensor Networks, INCoS, 2009, pp. 233-236. PDF

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors, CASES, 2008, pp. 197-206. PDF

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency, DAC, 2008, pp. 68-71. PDF

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits, ICCD, 2008, pp. 699-706. PDF

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors, LCTES, 2008, pp. 71-78. PDF

Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices, ICSAMOS, 2008, pp. 124-131. PDF

A centralized cache miss driven technique to improve processor power dissipation, ICSAMOS, 2008, pp. 124-131. PDF

Error-Aware Design, DSD, 2007, pp. 8-15. PDF

Limits on voltage scaling for caches utilizing fault tolerant techniques, ICCD, 2007, pp. 488-495. PDF

Solutions to a Complete Web Service Discovery and Composition, CEC/EEE, 2006, pp. 73. PDF