Research @ Inano: The major focus of our research is interfacing and integrating nano-structures in devices, circuits and systems. The work centers around several interrelated areas of nanoscale materials and devices.
- integrating nanowires in devices and circuits employing processes compatible with mass-manufacturing,
- nanofabrication processes for molecular scale electronics devices for high device yields, and
- application of nano-structures in modulating the index of metamaterials between negative and positive values.
We also work on developing MEMS based fabrication technologies for 3D isotropic metamaterials and study the impact of nano-particles in plant and animal health.
Nanowires Integration for Electronics, Photonics, Sensors, MEMS and NEMS
In the next decade, the forty-year miniaturization revolution in silicon-based microelectronics will approach its ultimate, nanometer-scale limits due to the extreme economic and technological barriers facing the traditional approach to fabricating higher density perfect devices. Now it has become increasingly urgent and crucial for scientists to develop alternative nano-materials and devices to enhance or supplant silicon-based devices. At the same time it is widely accepted that photons will replace electrons as a successor technology for communications. My work covers both of these important areas. In 2004, we demonstrated a novel bridging technique that addresses the long-standing challenge of integrating semiconductor nanowires in devices and circuits. The technique allows individual electrical access to a large number of nanowire devices without recourse to nanoprobes or tedious and expensive serial interfacing procedures. We also employed the bridging technique to synthesize optically active semiconductor (III-V) nanowires on silicon (or group IV) wafers. This opens exciting opportunities for light emitters and detectors on silicon surfaces for applications in intra-chip and inter-chip optical communications.
Nanoepitaxy: Nanoscale semiconductor structures with two or three of their dimensions at the nanometer scale are rich in fundamental issues and promise revolutionary new device concepts. Homo and heterogeneous synthesis of nanomaterials on lattice-matched and mismatched substrates have revealed a wealth of interesting properties and dramatic enhancements of magnetic, electrical, optical, and other properties. Devices fabricated from these nanoscale structures offer significantly improved photonic and electronic performance and, because of their small footprint, are candidates for device level integration with Si CMOS technology. For example, lattice strain, which strictly limits composition and thickness in 3D and 2D semiconductor heterostructures, can be significantly relaxed at the nanoscale thus permitting a wider range of materials and properties, and in some cases strain can be used as a tool to dictate the lateral dimensions and spatial ordering of epitaxial nanostructures. Furthermore, recently demonstrated branched heterostructures obtained by controlled surface nucleation can lead to novel interconnect and device concepts. To fulfill these tremendous potential many technological barriers however must still be overcome.
Granted that the technological momentum is pushing for the incorporation of nanostructures in devices, integrated circuits (ICs), and systems and that the technology is there to synthesize diminishingly small nanostructures such as nanodots, nanowires, molecules or nanotubes, it becomes obvious that we must now look for ways to take advantage of them in solving pressing issues in electronics, photonics, defense, energy conversion, sensing, and biomedical applications. At Davis, I am looking into the basic technological challenges in developing mass-manufacturable fabrication processes for devices and circuits with nanowires, nanodots and organic molecules. We use a Chemical Vapor Deposition (CVD) reactor to grow Si, SiGe, SiGeC and some III-V and oxide nanowires. With the many methods of synthesizing nanostructures of different materials, size and shape and numerous single device demonstrations, we see the nanodevice research of today as not so much “how to demonstrate a novel application of nanostructures with a single device” but instead “how to develop the massively parallel, manufacturable and reproducible fabrication and incorporation of dense, low-cost nano-device arrays in highly integrated material systems”.
A significant roadblock to wide-scale integration of functional nanowire-based devices is the difficulty in forming contacts to the nanowires. A scheme aimed at integrating nanowires in devices and circuits should be "universal", compatible with current IC processing methods, and cost-effective. In addition, precise control on the nanowire length, reliable and low contact resistance, and good mechanical robustness will be highly desirable. To date, many reported techniques for fabricating nanowires in controlled and reproducible fashion did not meet most of the above-mentioned requirements and a dramatically new approach is needed for integrating nanowires with conventional circuitry. With our bridging technique, we successfully demonstrated two order of magnitude lower contact resistance than that of any reported work and this is as good as NiSi contacts for planar Si technology. With our collaborators at HP Labs and UC Santa Cruz, we recently fabricated the fastest nanowire based photodetector with a FWHM of 14ps pulse response. The most attractive feature of this device is the fact that it was fabricated on an anamorphous substrate (more info).
Molecular Scale Electronic Devices:
We were the first to report a dramatic improvement in the yields of molecular scale electronic devices by using ultrasmooth metal electrodes with better than 1Å RMS roughness. An impressive 100% device yield in the molecular devices made of LB monolayer and ~35% yields in the devices made with SAM monolayer with device sizes varying from 1μmx5μm to as big as 20μmx5μm were observed. Initially we started with a chemical mechanically polishing (CMP) for preparing ultra-flat surfaces and subsequently developed controlled metal pressing methods and a self assembly method of generating ultra-smooth metal film by using a wetting layer during the evaporation of metals (a method that will offer a large wafer with ultra-flat metal surfaces).
Fabrication of molecular scale electronic devices generally involves deposition of a metal top electrode onto an organic film. During the evaporation process, high energetic granules of metals may lead to unwanted reactions between the organic molecules and deposited top electrodes. This can cause, as commonly reported, lasting damage which leaves most junctions either short or open. To overcome this important issue of physical damage to the molecules, we developed a novel technique of interfacing molecules by laying prefabricated metallic electrodes on top of a monolayer of molecules. This powerful technique can be used to interface large arrays of switching junctions and as a test-vehicle for accurate characterization of the molecular properties without causing any damage during the device fabrication process (more info).
Devices and Applications of Negative Index Materials:
The idea of materials with a negative refractive index opens up new conceptual frontiers and opportunities in photonics. Unusual properties of negative index materials (NIM) offer breakthrough applications including imaging of ultra-small features with details finer than the wavelength of light used. We initiated a research program in this exciting field in collaboration with several scientists at Hewlett Packard Labs, UC Berkeley and UIUC. We proposed and demonstrated a NIM based devices for ultra-fast switching and modulation of electromagnetic waves using photoconductive coupling of high-speed carriers. Our group also works on developing the low cost synthesis methods for 3D, homogeneous and isotropic NIM leveraging on MEMS and nano-imprinting along with micro self-assembly techniques (more info).
Some Scientific accomplishments of Inano Researchers:
- Demonstrated the Fastest Nanowire Based Photoconductors PDF.
- Developed a technique for dynamically switching between positive and negative permeability of metamaterials by photoconductive coupling for modulation of electromagnetic radiation PDF.
- First demonstration of an Atomic Switching Junctions based on solid electrolytes and an organic monolayer of Molecules.
- First demonstration of ultrahigh-density semiconductor nano-bridges formed between two semiconductor surfaces (Si, ZnO and InP nano-bridges on Si) PDF1, PDF2, PDF3.
- Demonstrated a MEMS based fabrication technique for 3D negative index materials PDF.
- Developed a novel technique for the synthesis and positioning of metal and alloyed nanoparticles with uniform size, shape and periodicity in order to synthesize well ordered nanowire arrays PDF.
- Demonstrated techniques for generating the smoothest metal surface with atomic scale flatness for molecular electronics and showed 100% device yields in molecular junctions with a Langmuir-Blodgett monolayer PDF1, PDF2.
- Developed a minority outreach program with some outstanding successes.
- Achieved world record in high linear photocurrents in photodetectors and demonstrated record 43dB noise suppression with distributed balanced photodetectors PDF.
- Demonstrated the first Resonant Cavity Enhanced Schottky Photodiode PDF.
1. Logeeswaran VJ, Ataur Sarkar, M. Saif Islam, Nobuhiko P. Kobayashi, Joseph Straznicky, Xuema Li, Wei Wu, Sagi Mathai, Michael R.T. Tan, Shih-Yuan Wang and R. Stanley Williams, "A 14 ps full width at half maximum high-speed photoconductor fabricated with intersecting InP nanowires on an amorphous surface", Appl. Phys A, 91, 1–5), 2008 (Invited) PDF
In this paper, we demonstrate a high-speed polarization-insensitive photoconductor based on intersecting InP nanowires synthesized between a pair of hydrogenated silicon electrodes deposited on amorphous SiO2 surfaces prepared on silicon substrates. A 14-ps full width at half maximum de-embedded impulse response is measured, which is the fastest reported response for a photodetector fabricated using nanowires. The high-speed electrical signal measurements from the photoconductor are performed by an integrated coplanar waveguide transmission line. The demonstrated ability to grow intersecting InP nanowires on hydrogenated microcrystalline Si surfaces will facilitate the construction of ultra-fast photodetectors on a wide range of substrates.
The demonstrated ability to grow intersecting InP nanowires on microcrystalline Si surfaces is a step forward in the construction of ultra-fast photodetectors in III–V nanowires on a wide range of substrates.
2. Anurag Choudhry, Vishwanath Ramamurthi, Erin Fong and M. Saif Islam , “Ultra-low contact resistance of epitaxially interfaced Si nanowires, Nano Letters, vol. 7, pp. 1536-1541, 2007. Link: 10.1021/nl070325e
In this paper we presented the results of fabrication and characterization of a large number of bridging nanowires for extracting their contact resistance. We used SEM, for measuring the physical dimensions and a semiconductor parameter analyzer for measuring their current voltage characteristics. A model was built to interpret and analyze the data. We successfully demonstrated at least two order of magnitude lower contact resistance than that of any reported work and this is as good as NiSi contacts for planar Si technology. We also have published papers describing mechanical, physical interfaces and heteroepitaxial properties of nanowires. We are developing bridging mechanism for a number of Oxide nanowires including ZnO, In2O3 and SnO2.
Unlike the research-based approach of sequentially connecting electrodes to individual nanowires for device physics studies, we developed nano-bridging - a massively parallel and mass-manufacturable interfacing technique for reproducible fabrication of dense and low-cost nanodevice arrays. This paper shows that our approach of integrating nanowires offers the lowest reported contact resistance for nanowires. Individual electrical access to a large number of nanowire devices without recourse to nanoprobes or tedious and expensive serial interfacing procedures ensuring ultra-low contact resistance is reported in this paper. Erin Fong, one of our undergraduate researchers, has participated in this research and significantly contributed to this work.
3. Logeeswaran VJ, Alexander N. Stameroff and M. Saif Islam, Wei Wu, Alexander M. Bratkovsky, Philip J. Kuekes, Shih-Yuan Wang & R. Stanley Williams “Switching Between Positive and Negative Permeability by Photoconductive Coupling for Modulation of Electromagnetic Radiation”, Appl. Phys. A 87, 209–216 (2007). PDF
We are developing novel methods for switching the index of "Metamaterials" between positive and negative values. In this paper, we theoretically introduce modulation mechanism for metamaterials by means of photoconductive couplings. A photosensitive material is proposed to be deposited in the gap of the split ring resonator (SRR) structure. The photo-induced electron–hole plasma in a semiconductor interacts with the electromagnetic wave by switching the SRR into a closed metal loop which is not a resonant structure for the frequency under consideration thus modulating the permeability between negative and positive values when the electron–hole plasma reaches an appropriate level. We also proposed a new type of modulating device for the first time based on the proposed modulation mechanism.
The results of this paper are very important for designing a novel modulator for switching and modulating electromagnetic waves using metamateris. Based on the results of this paper, we are currently working on using photo-active semiconductors and semiconducting nanowires to induce photoconductive couplings. In such a device, the optical characteristics are engineered – and are not dependent on bandgap of semiconductor and thus offer high potential for easy integration on silicon wafer. This opens an opportunity for modulation on Si surface. We plan to implement this technique not only in 1D but also in 3D metamaterials that we are also fabricating using a MEMS based technique.
4. Logeeswaran VJ, Mei-Lin Chan, Y. Bayam, M. Saif Islam David A. Horsley, Wei Wu, Shih-Yuan Wang and R. Stanley Williams “Ultra-smooth metal surfaces generated by pressure induced surface deformation of thin metal films”, Appl. Phys. A 87, 187–192 (2007). PDF
This paper addresses an important issue of surface roughness on metal thin films. In the past, we conducted a large number of measurements to investigate the surface roughness of freshly deposited Pt films using atomic force microscopy (AFM) and observed a root-mean square (RMS) roughness of 7Å with high density of grains and spikes more than 5nm in length. We then We developed and applied a chemical-mechanical polishing (CMP) process to achieve ultra-smooth Pt surfaces with less than 1Å RMS roughness and observed a dramatic improvement in the device yield in the molecular devices (almost 100% for LB monolayer and ~35% SAM monolayer). Inspired by these results, we tried to address the issue of surface scattering in metamaterials. We quickly realized that CMP cannot be used for superlenses based on metamaterials and alternative methods are needed. This paper implements our idea of pressing Ag films for making them smooth. We used the HP Labs resources for the delicate experiments and characterizations. The results are extraordinary. We were the first to demonstrate better than 1Å RMS roughness in the Ag film.
The paper offers a practical method of generating ultra-flat surfaces for many different applications including molecular electronics, plasmonics and metamaterials. This work led to another great development in our group - a self assembly method of generating ultra-smooth metal film by using a wetting layer during evaporation.
5. I. Kimukin, M. Saif Islam and R. Stanley Williams, “Surface depletion thickness of p-doped Si nanowires grown using metal-catalyzed chemical vapour deposition”, Nanotechnology 17 (2006) S1–S6. PDF
We developed a room temperature anisotropic wet chemical etching technique to gradually reduce the diameter of a Si nanowire and subsequently measured the current-voltage characteristics to evaluate the depletion region thickness across the radius. In our bridging nanowires, a surface depletion thickness of ~25nm for a doping concentration of 10^18/cm3 was measured. This corresponds to a surface charge density of ~2.6 × 10^12 cm−2. We also found the etching rate of Si nanowires to be at least 10 times faster than bulk Si in some wet chemical etchants.
The presence of a surface depletion region shows that we cannot arbitrarily shrink the diameter of a nanowire because of a finite depletion region. Different surface treatments will help vary the thickness of the depletion region and the work demonstrates the importance of understanding and controlling the surface properties of nanowires. An understanding of the doping distribution in nanowires is crucial for accurate prediction of the device parameters such as Vth or break-down voltage of a nanowire transistor. We are now using our diameter reduction mechanism to profile doping concentration across the radius.
6. S. Reza, G. Bosman, M. Saif Islam , T. I. Kamins, S. Sharma and R. Stanley Williams, “Noise in Si Nanowires”, IEEE Trans. Nanotechnology, 5, No. 5, p523 2006. PDF
In this paper, we report our characterization work on the 1/f noise of bridging nanowires and compared them with that of carbon nanotubes (CNTs). The noise data shows at least two order of magnitude better performance in the bridging nanowires than that of CNTs due to highly epitaxial bonding between bridging nanowires and electrodes. These results substantiate our endeavor for employing the bridging techniques for designing nanowire based electronic and photonic devices.
The noise is the random fluctuating component of a voltage or current in a device, which can be caused by different mechanisms for example, carrier mobility fluctuation, carrier trapping–detrapping etc. The noise measurement can yield a lot of information about the manufacturing process and the inner workings of a device. For example the 1/f noise in a MOSFET is related to the impurity related trap density at the oxide interface and can be used to identify problems in the manufacturing process. The noise characterization for the modern nanoscale devices is even more important because they typically operate at a lower voltage so the signal-to-noise ratio (SNR) is critical. Currently, carbon nanotube (CNT) is the most promising technology in the mesoscopic device area. In the beginning, it was expected that the nanotubes would be relatively less ‘noisy’, because of the stable carbon-carbon bonds. But it came as a big surprise when it was shown that the opposite is true, they are very noisy. Similarly, the noise level of nanowire based devices fabricated using the existing research based interfacing method (metal evaporation on nanowires) is also very high. The ultra-low noise property of our bridged nanowires makes the bridging technique a preferable one for interfacing nanowires.
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