// prob1_ref.v
// 15-input adder for single-bit inputs (0=-1, 1=+1)
// Reference version to verify calculations in hardware version
//
// Do not even think about synthesizing this module!
//
// Notes:
//  - There is no delay in this module so the answer will immediately
//    appear at the module's output when an input changes.
//  - This code is not complete and is meant to possibly be a useful
//    starting point.  If it is not helpful, then don't use it!
//
// 2013/01/17  Updated
// 2009/01/23  Updated
// 2005/01/21  Written, shell only

`timescale 10ps/1ps
`celldefine
module prob1_ref (
   in,
   out
   );

   // Module I/O declarations
   input [14:0]		in;
   output [9:0]		out;    // 10 bits wide

   // Module variable declarations
   reg signed [9:0]	out;    // Don't use "signed" in synthesized code
                                //   but it is ok in this test code.
   integer              count;

   // Main logic
   always @(in) begin
      out = 0;

      for (count=0; count<=14; count=count+1) begin
         if (in[count] == 1'b0)
            out = out - 1;
         else
            out = out + 1;
      end
   end

endmodule
`endcelldefine