Department of Electrical and Computer Engineering


Digital Systems I: Winter 2002


Prof. Vojin G. Oklobdzija

Office: Engineering II, Room 3007

Office Hours: 3-4 M, Room 3007, e-mail appointed preferred (please see the appointment policy)

Times and Location

5:00-6:30 M-W, 179 Chemistry

Teaching Assistants:


Name Marko Aleksic  Gabriel Aguirre  Hardik Gandhi  M. Wang
Office Hours Th  12:30-1:00pm W 6:30-7:00pm M 6:30-7:00pm T 6:30-7:00pm 
Office Location 2110 2110 2110 2110


Michael Schwartz


Course Information

Lab Information



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You are responsible for watching the web site for the information about the course

Related Links: 

Here are the links to the first two chapters of C. H. Roth's book "Fundamentals of Logic Design"  - you can read from them until your textbook arrives:
Here are Roth's lectures ECE316 (EEC180A) from the University of Texas at Austin.
You can watch them using Real Video:    Click Here


UC Berkeley: 

Design Techniques and Components for Digital Systems

Stanford University

EE 121: Digital Design Laboratory

EE 183: Advanced Logic Design Laboratory

EE 271: Introduction to VLSI Systems

Course Information

Course Outline

Course Overview, Reading Assignments, and Homework Assignments


Notes on Memory and Programmable Logic

Final - Solutions

Midterm and Solution:

Midterm 1 Solution

Homework Solutions:

Online Grade Posting 

Posted by last four digits of Student ID Number

Lab Report Scores

Quiz Scores

Homework Scores

Midterm Scores

Final grades

Lab Information

Places to Purchase Protoboards

Laboratory Guidelines

Lab report Guidelines

Lab Report Coversheet

Special Information on Use of Saturday Lab Sections


Lab 1, Introduction to Lab Instruments

Lab 2, Introduction to Altera Design System

Lab 3, Combinational Network Design Using Algebraic Simplification

Lab 4, Combinational Network Design

Lab 5, Combinational Network Design Using MSI and PAL Devices

Lab 6, Flip-flops and Latches

Lab 7, Counter Design

Lab 8, Sequential Circuit Design

Lab 9, Arithmetic Circuit Design



AMD PALCE 22V10 Datasheet

Fairchild Semiconductor Catalog

Fairchild Semiconductor DM74LS00 Datasheet

Fairchild Semiconductor DM74LS02 Datasheet

Fairchild Semiconductor DM74LS04 Datasheet

Fairchild Semiconductor DM74LS10 Datasheet

Fairchild Semiconductor DM74LS20 Datasheet

Fairchild Semi conductor DM74LS73A Datasheet

Fairchild Semiconductor DM74LS74A Datasheet

Fairchild Semiconductor DM74LS83A Datasheet

Fairchild Semiconductor DM74LS125A Datasheet

Fairchild Semiconductor DM74LS153 Datasheet

Fairchild Semiconductor DM74LS245 Datasheet

Fairchild Semiconductor DM74LS257B Datasheet

Fairchild Semiconductor DM74LS283 Datasheet

Fairchild Semiconductor DM74LS373/DM74LS374 Datasheet

HP 5082-7730 Seven Segment Display Datasheet 



Schedule of the Lectures

Schedule of the Labs

Homework Assignments

Week 1: Jan. 7-11

Reading: Chpt. 1 
Course overview, The Process of Design, Digital Hardware Systems: 
- review of logic design, nuber systems and number representation, arithmetic operations with binary numbers.

No Labs

Homework 1:

Chpt.1, Probl: 1.1-1.10

Week 2: Jan. 14-18 

Reading: Chpt. 2, 3 
Boolean Switching Algebra
- Boolean Algebra, introduction, basic theorems
- Expressions, laws, positive and negative logic

Lab 1:

Intorduction to lab instruments and work environment

Homework 2:

Chpt.2, 3, Probl: 2.1-2.6 and 3.3-3.9

Week 3: Jan. (21*)-25  *Holiday

Reading: Chpt . 4, 5 
Boolean Algebra:
- Algebrtaic Simplifications 
- Applications of Boolean Algebra 
- Minterm and Maxterm expansions 
- Gate Logic, Implementations

Lab 2:

Introduction to Computer Aided Design: 
Altera design system: tutorial

Homework 3:

Chpt.4,5, Probl: 4.4-8, 5.1, 5.2, 5.9, 5.21-24.

Week 4: Jan. 28-Feb.1  

Reading: Chpt. 6, 8 
Minimization Tools:
- Karnaugh Maps 
- Multi-level Gate Networks 
- Implementation wiht NAND and NOR gates

Lab 3:

Combinational Network Design using Algebraic Simplifications

Homework 4:

Chpt. 6,8, Probl: 6.5-6.12, 8.1-8.7.

Week 5: Feb.4-8

Reading: Chpt. 9, 10
MSI, Programmable and Non-Gate Logic
- Multiplexers, Decoders 
- ROM and PLA (PAL) 
- Design of combinational networks

Lab 4:

Combinational Network Design using Karnaugh Maps

Homework 5:

Chpt. 9, 10, Probl: 9.1-5, 9.20-21, 10.1-4, 10.14.

Week 6: Feb. 11-15

Reading: Chpt. 11,12 
Memory Elements, use of Memory Elements in the design:
- Flip-Flop Circuit: D, R-S, J-K, T 
- Clocking, Edged Triggered, Level Sensitive 
- Master-Slave Latch 
- Timing and Clock Distribution 
- Counters and sequential networks

Lab 5:

Combinational Network Design using Multiplexers and PALs

Homework 6:

Chpt. 11,12, Probl: 11.3-6, 11.13, 12.1-4, 12.14-15.

Week 7: Feb. (18*)-22   *Holiday

Reading: Chpt. 13, 14 
Sequential Logic Design
- Analysis of Clocked Sequential Networks 
- State Graphs and Tables 
- Derivation of State Graphs and Tables 
- Different FF realizations 
- Examples

Lab 6:

Flip--Flops and Latches

Homework 7:

Chpt. 13, 14, Probl: 13.2-5, 14.13-16.

Week 8: Feb. 25-March 1.

Reading: Chpt. 15, 16 

Sequential Networks Design
- Reduction of State Tables 
- State Assignment 
- Guidelines for State Assignment 
- Practical examples

Lab 7:

Design of Counters

Homework 8:

Chpt. 15, 16, Probl: 15.1-5, 16.1-2.

Week 9: March 4-8  

Reading: Chpt. 18, 19 
Sequential Logic using MSI and PLDs
- Registers and Counters 
- Design using Counters 
- Register Transfer and 3-state Logic 
- Finite State Machine Design using ROMs and PLAs and PALs 
- Programmable Gate Arrays: PGAs and FPGAs

Lab 8:

Sequential Network Design

Homework 9:

Chpt. 18, 19, Probl: 18.2, 18.5-6, 18.8, 19.1, 19.7.

Week 10: March 11-(15*) *Monday class 

Reading: Chpt. 20 
Arithmetic Circuits
- Networks for Addition/Subtraction 
- Binary Adders: RCA, CLA 
- Multiplication / Division 
- ALU Design

Lab 9:

Arithmetic Circuits

Homework 10:

Chpt. 20, Probl: 20.9-12.




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(Page last modified:04/09/2002  Wednesday, 09-Jan-02 15:28:52)