EEC 281 Design Compiler Notes

A few Design Compiler Clarifications, Pitfalls, and Suggestions

Design Compiler prints combinational and sequential (i.e., non-combinational) circuit area into the *.area file. The units for area are specified by the design library. However, the units used by the library we are using are currently uncertain—we have contacted the library's authors and even they are not sure(!). The absolute units are actually not important for our work and they are close to what we would expect in square microns (um^2) so assume these are the units for area.
Compile your design in ncverilog (or vcs) before synthesizing it because Design Compiler may not tell you a thing even if your design has a serious verilog problem!
Don't set the same register in more than one always block--the resulting operation can be ambiguous and DC will give you an error.
If you get a warning or error and can't figure out the cause or solution, please:
1. Ask your nearby study partner if they know a solution
2. Paste the message into Google and see if anything pops up
3. If you've tried a few things and can't fix it send me an email
4. If you fix something that would also improve the dc_compile script referenced here, please let me know!
Do not use signal strengths or primitives in verilog to be sythesized.
Even if your design is purely combinational, add a "clk" input port to get rid of a few warning messages. Things will compile correctly (though the timing may be off) in either case.
(Disk quota exceeded)
Use the following commands to find what is taking up your disk space: du and man du. Email ece support to find out more details about your quota. In one case, a .cache/ directory used up a lot of unnecessary space.
Warning: Can't read link_library file 'your_library.db'. (UID-3)
Verify your .synopsys_dc.setup files (in your current working dir and/or home dir) are correct.
Error: Current design is not defined. (UID-4)
Design Compiler does not know which module to synthesize. Check the modules set in the elaborate and current_design commands.
SEQGEN in your .vg output file
The SEQGEN message is printed when Design Compiler cannot find a valid technology library (for example, caused by a problem with the .synopsys_dc.setup file). From the design compiler manual: "The RTL is translated into a technology-independent representation called SEQGEN; the SEQGEN is then mapped to gates from the technology library"

Design Compiler Files and Example Design

Makefile
Contains all commands needed for simulation and synthesis. You must enter the top-level design name at the top of the file.
Type "make <return>" to see make targets and instructions.
dc-template.tcl
Template used to generate a customized command file for Design Compiler. Do not edit this file unless you are told you need to.
.synopsys_dc.setup Don't miss this one! Make sure the file begins with a period. Copy it to your home dir (but then you can't customize it for individual runs, which is probably ok), or your working dir (make sure you copy it when you start a new dir). If you have a .synopsys_dc.setup file in your home directory (from ECE 180B for example), you will likely need to move it or change its name so that DC won't get confused.
Do not edit this file unless you are told you need to. Remember that it appears in linux only with "ls -a" and not just "ls".
abc.v
Very simple example design with 2-bit and 32-bit adders, and registers
def.v
Very simple example submodule of abc.v with 2 FFs.
abc.vfv
File that contains all source verilog files for simulation (NCVerilog or Verilog-XL).
abc.vfs
File that contains all source verilog files for synthesis (Design Compiler) of abc.v. Note: never include test files.
abc.vt
Very simple test bench file for abc.v and def.v that compiles cleanly.
Finite state machine example from slides.
- fsm.v
- fsm.vfs File that contains all source verilog files for synthesis (Design Compiler) of fsm.v. Note: never include test files.
Super simple OR example from synthesis slides.
- or2.v
- or2.vfs File that contains all source verilog files for synthesis (Design Compiler) of or2.v . Note: never include test files.
- or2.vfv

Configuration changes you must make

clock cycle time
file: dc-template.tcl
command: set clk_period CLKPERIOD" (CLKPERIOD in units of nanoseconds)
Leave at default value unless told to change it.

Finding the maximum possible clock frequency (minimum cycle time)

Set the clock period to a very short cycle time such as 0.1 ns (10 GHz)
Synthesize the design
Unless the circuit is extremely simple, there will be a negative slack result. Use the equation in the handout to calculate the minimum achievable clock cycle time.

Finding the minimum possible circuit area

Set the clock period to a very long cycle time such as 1000 ns (1 MHz)
Synthesize the design
Unless the circuit has an extremely long logic depth between pipeline registers, there will be a positive slack result. The area result is the minimum achievable circuit area.

The Standard Cell Library We Use

We currently use the 45 nm NanGate FreePDF45 Open Cell Library (http://www.nangate.com/?page_id=2325) which is an open-source library developed by NanGate Inc, http://www.nangate.com

It contains "62 different functions ranging from buffers to scan flip-flops with set and reset, including specialized low power cells with multiple drive strength variants, the library includes over 170 different standard cells."

Timing parameters are in units of nanoseconds.

Datasheet.typical.corner.pdf
Details of the standard cells for Typical speed NMOS, Typical speed PMOS, Vdd = 1.1 V, and T_j = 25.0°C.
Datasheet.pdf
Details of the standard cells for five corners:
1. typical,
2. slow (slow, slow, Vdd = 0.95 V, T_j = –125°C),
3. fast (fast, fast, Vdd = 1.25 V, T_j = –0°C),
4. worst_low (worst.low, worst.low, Vdd = 0.95 V, T_j = –40.0°C), and
5. low_temp (low.temp, low.temp, Vdd = 1.25 V, T_j = –40.0°C).
NangateOpenCellLibrary.v
The file that specifies the logic and the rise and fall times (by the specify block) of the standard cells.

Previously, we used the 0.25 um vtvt library.

TSMC

MOSIS

Virginia Tech VLSI for Telecommunications web page

Building the .db file

 (1) lc_shell
 (2) read_lib NangateOpenCellLibrary_typical_ccs.lib
 (3) write_lib NangateOpenCellLibrary -output NangateOpenCellLibrary.db
     OR: 
     write_lib NangateOpenCellLibrary -format db

Running a Simulation Using Your Synthesized Gates (NO LONGER SUPPORTED)

vtvtlib25.v

/net/pizza/tools/classes/281/lib/vtvtlib25.v

To simulate with gates, add something similar to the test_prac_gates target to your Makefile shown below. The test_prac target is an example of how the test would normally be run with the source verilog files.

test_prac_gates:
        ncverilog [flags_normally_used] /net/pizza/tools/classes/281/lib/vtvtlib25.v prac.vg prac.vt

test_prac:
        ncverilog [flags_normally_used] prac.v prac.vt

prac.vg

prac.vt

Digging deeper into DC

Design Compiler

Synopsys

sold &

Two other tools by Synopsys can be used to graphically interact with DC and view netlists.

design_vision
design_analyzer

You can also compile your design within design_vision by loading file using the analyze menu and then using the same dc_compile script. It will complain about the /* */ comments in the script file when run this way. It also complains about a "your_library.db" but both can apparently be ignored.

Design Analyzer seems to be not working correctly.

Odd Things That Should Be Fixed

report_power sometimes gives a warning message:
Warning: Sequential cell foo with no output activity annotation. (PWR-81)
It seems like set_switching_activity should fix it, but the annotated inputs don't propagate and the warning persists. I don't think it affects the power estimate(?).
When instantiating a large structure (e.g., a 32-bit adder), DC plugs in a module (presumably from some library it has) and I can't get it to flatten the output verilog netlist. ungroup doesn't do it. Area and power numbers seem ok in any case.

EEC 281 | B. Baas | ECE Dept. | UC Davis
Written by Bevan Baas with valuable help from Gabriel Ricardo, Bart Zeydel, Eric Work, Zhibin Xiao, Jon Pimentel, and Shifu Wu.

2025/01/13  Minor edits
2021/02/08  Added or2.v example, updated Makefile and dc-template.tcl
2020/03/03  Added fsm.v and fsm.vfs
2020/02/07  Added sections to find max clock frequency and minimum area
2017/02/04  Major changes for new NanGate 45 nm library
2015/02/03  Added SEQGEN note
2015/01/16  Minor changes
2010/02/17  A few small changes
2010/02/16  Updated path to vtvtlib25.v
2009/02/13  Some updates