Project Title

CAREER: A Comprehensive High-Level Design Validation Approach for Microprocessors

Project Summary

This project concentrates on a career development plan for integrating research and teaching in the field of design validation. The research component focuses on devising practical methods for high-level design validation of microprocessors and supporting CAD tools based on explicit design error modeling, design error simulation, model-directed test generation, and design error correction. Specifically, the research concentrates on the following issues: (a) the development of a high-level design error simulation method based on a new high-level critical path tracing approach; (b) the establishment of high-level controllability and observability measures that can be used to guide the test generation for design errors; (c) the development of high-level test generation algorithm(s) that generate instructions to detect modeled and actual high-level design errors in microprocessors; (d) the development of high-level design error location, diagnosis, and correction methods that pinpoint the error location and suggest ways to correct it; and (e) the formation of a set of guidelines that facilitate design for validation and post-silicon validation. The teaching component concentrates on enhancing the undergraduate and graduate programs in our department by introducing new graduate and undergraduate courses on design verification and incorporating current research results into them, active mentoring of undergraduate students, effective supervision of research for graduate and undergraduate students, active collaboration with the computer industry, and outreach activities to freshmen students as well as undergraduate students at the national level.


Faculty: Hussain Al-Asaad
Current Student: Jorge Campos
Former Students: Idis Woods, Lourdes Ramirez, Raymond Lee, Ganesh Valliappan, Hector Arteaga

Teaching Outputs

Course Development:

bulletUndergraduate Course: EEC183 - Testing and Verification of Digital Systems.
bulletGraduate Course: EEC283 - Advanced Design Verification of Digital Systems.

Research Outputs

bulletJ. Campos and H. Al-Asaad, "A novel mutation-based validation paradigm for high-level hardware descriptions", to appear in IEEE Transactions on VLSI, 2008.
bullet Jorge Campos, MVP: A Mutation-based Verification Platform, Ph.D. Thesis, UC-Davis, March 2007.
bulletH. Al-Asaad, "Efficient global fault collapsing for combinational library modules”, Proc. International Conference on Computer Design (CDES) , 2007, pp. 37-43.
bulletJ. Campos and H. Al-Asaad, “Circuit profiling mechanisms for high-level ATPG”, Proc. Microprocessor Test and Verification Workshop, 2006, pp. 9-14.
bulletH. Al-Asaad, "AGFC: An approximate simulation-based global fault collapsing tool for combinational circuits", Proc. International conference on Circuits, Signals, & Systems, 2006, pp. 248-253.
bullet Hector Arteaga, Increasing Observability in Modern Microprocessors, M.S. Thesis, UC-Davis, March 2006.
bulletJ. Campos and H. Al-Asaad, “Search-Space Optimizations for High-Level ATPG”, Proc. Microprocessor Test and Verification Workshop, 2005, pp. 84-89.
bullet J. Campos and H. Al-Asaad, “MVP: A Mutation-Based Validation Paradigm”, Proc. International High-Level Design Validation and Test Workshop, 2005, pp. 27-34.
bullet H. Al-Asaad, “EGFC: An Exact Global Fault Collapsing Tool for Combinational Circuits”, Proc. International  conference on Circuits, Signals, and Systems, 2005, pp.56-61.
bullet Ganesh Valliappan, Boundary Testing: A Low Cost Test Generation Method for Combinational and Sequential Circuits, M.S. Thesis, UC-Davis, August 2005.
bulletH. Al-Asaad, G. Valliappan, and L. Ramirez, “A Novel Functional Testing and Verification Technique for Logic Circuits”, Proc. International Conference on Computer Design (CDES), 2005, pp. 129-135.
bulletH. Arteaga and H. Al-Asaad, “On Increasing the Observability of Modern Microprocessors”, Proc. International Conference on Computer Design (CDES), 2005, pp. 91-96.

J. Campos and H. Al-Asaad, “Mutation-Based Validation of High-Level Microprocessor Implementations”, Proc. International High-Level Design Validation and Test Workshop, 2004, pp. 81-86.


J. Campos and H. Al-Asaad, “Concurrent Design Error Simulation for High-Level Microprocessor Implementations”, Proc. Autotestcon, 2004, pp. 382-388.


H. Arteaga and H. Al-Asaad, “Approaches for Monitoring Vectors on Microprocessor Buses”, Proc. International Conference on VLSI, 2004, pp. 393-398.


H. Al-Asaad and R. lee, “Simulation-based approximate global fault collapsing”, Proc. International Conference on VLSI, 2002, pp. 72-77.

bulletLourdes Ramirez, Component Level Functional Verification, M.S. Thesis, UC-Davis, December 2001.


Gate-Level Error Simulator: ESIM.

Global Fault Collapsing Tools: AGFC and EGFC.

Related Links

bulletDepartment of Electrical and Computer Engineering
bulletUniversity of California - Davis
bulletNational Science Foundation

Acknowledgment and Disclaimer

This web page is based upon work supported by the National Science Foundation under Grant No. 0092867. Any opinions, findings and conclusions or recommendations expressed in this web page are those of the authors and do not necessarily reflect the views of the National Science Foundation (NSF).

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Last updated: 09/01/05.