EEC280: Advanced Logic Design

Prof. Vojin G. Oklobdzija
Electrical and Computer Engineering Department
University of California
Davis

Content of the Course:

This course consists of a set of lectures dealing with topics and issues in design of complex and high-performance systems. Those issues range from dynamic and differential logic circuits to contemporary sub-micron circuit techniques.

The lecture starts with a set of papers on advanced circuits and logic. They include fundamental papers on dynamic and differential CMOS circuits which are currently used in high performance processors. The section is followed by a set of papers on differential pass-transistor logic which has been gaining importance in deep sub-micron technology.

The next set of lectures is dedicated to low-power techniques which is becoming a must not only in mobile and portable environment but are equally important issue in high-performance processor design. Recent developments in circuits and logic were presented in this set consisting of papers which are addressing the objective of satisfying low-power requirements. Attention has also been given to the adiabatic logic and development of the logic family applicable for adiabatic computation.

Next section deals with the system clocking issues, clock distribution techniques and latch design. It contains papers dealing with timing issues in high performance systems such as synchronization, handling of clock skews, design of a fast latch and power saving techniques. Pipelining techniques with the aim of achieving high performance are also addressed.

The section on VLSI algorithms and computer arithmetic shows relationship between implementation techniques, choice of the appropriate algorithm and logic technology. The goal is to extract the benefits of both and achieve efficient and fast implementation. The section contains papers on fast and optimal implementation of ALU, parallel multiplier and MAC units that are a common building block of the Digital Signal Processing (DSP) systems. The presented work emphasizes the importance of appropriate algorithm and its proper mapping into the technology of choice.

This course is intended for a graduate student in electrical and computer engineering, but it is also a reference for the practicing engineer. It is intended to provide a useful and needed reference to a collection of accumulated experience necessary for a good and successful design.
 
 
 

List of papers covered in this course:
 

Advances in CMOS Circuits
 

  1. A. Masaki, "Deep-Submicron CMOS Warms Up to High-Speed Logic", IEEE Circuits and Devices Magazine, November 1992. Krambeck, C.M. Lee, H.S. Law, "High-Speed Compact Circuits with CMOS", IEEE Journal of Solid-State Circuits, Vol SC-13, No 3, June 1982.
  2. V.G. Oklobdzija, R.K. Montoye, "Design-Performance Trade-Offs in CMOS-Domino Logic", IEEE Journal of Solid-State Circuits, Vol SC-21, No 2, April 1986.
  3. N.F. Goncalves, H.J. DeMan, "NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures", IEEE Journal of Solid-State Circuits, Vol SC-18, No 3, June 1983.
  4. L.G. Heller, et al, "Cascode Voltage Switch Logic: A Differential CMOS Logic Family", in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984.
  5. L.C.M.G. Pfennings, et al, "Differential Split-Level CMOS Logic for Subnanosecond Speeds", IEEE Journal of Solid-State Circuits, Vol SC-20, No 5, October 1985.
  6. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.

 

    Use of Pass-Transistor Logic
 

  1. K. Yano, et al, "A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic", IEEE Journal of Solid-State Circuits, Vol 25, No 2, April 1990.
  2. K. Yano, et al, "Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
  3. M. Suzuki, et al, "A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic", in 1993 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1993.
  4. N. Ohkubo, et al, "A 4.4-ns CMOS 54x54-b Multiplier Using Pass-transistor Multiplexer", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
  5. V. G. Oklobdzija and B. Duchêne, "Pass-Transistor Dual Value Logic For Low-Power CMOS," Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
  6. F.S. Lai, W. Hwang, "Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems", Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995
  7. A. Parameswar, H. Hara, T. Sakurai, "A Swing Restored Pass- Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
  8. T. Fuse et. al, "0.5V SOI CMOS Pass-Gate Logic", Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.


    Low Power Computation
 

  1. A. Chandrakasan, R. Brodersen, "Minimizing Power Consumption in CMOS Circuits", IEEE Proceedings 1995.
  2. T. Kuroda and T. Sakurai "Overview of Low-Power ULSI Circuit Techniques", IEICE Trans. Electronics, E78-C, No.4, April 1995, pp.334-344, INVITED PAPER, Special Issue on Low-Voltage Low-Power Integrated Circuits.
  3. Y. Sasaki, et al, "Multi-Level Pass-Transistor Logic for Low-Power ULSIs", Proceedings of the 1995 Low-Power Symposium.
  4. U. Ko, P. Balsara, "High Performance, Energy Efficient Master-Slave Flip-Flop Circuits", Proceedings of the 1995 Low-Power Symposium.
  5. E. De Man, M. Schobinger, "Power dissipation in the Clock System of highly pipelined ULSI CMOS Circuits", Proceedings of the International Workshop on Low-Power Design, 1994.
  6. C. Nagendra, et al, "A Comparison of the Power-Delay Characteristics of CMOS Adders", Proceedings of the International Workshop on Low-Power Design, 1994.
  7. T. Sakuta, et al, "Delay Balanced Multipliers for Low Power/Low Voltage DSP Core", Proceedings of the 1995 Low-Power Symposium.
  8. C. Tan, et al, "Minimization of Power in VLSI Circuits Using Transistor Sizing, Input Ordering, and Statistical Power Estimation", Proceedings of the International Workshop on Low-Power Design, 1994.
  9. M. Horowitz, et al, "Low-Power Digital Design", Proceedings of the 1994 IEEE Symposium on Low-Power Electronics, 1994.
  10. H. Kojima, et al, "Power Analysis of a Programmable DSP for Architecture/Program Optimization", Proceedings of the 1995 Low-Power Symposium.
  11. J.S. Denker, "A Review of Adiabatic Computing", 1994 IEEE Symposium on Low Power Electronics, October 10-12, San Diego, California.
  12. A. Kramer, et al, "2nd Order Adiabatic Computation with the 2N-2N and 2N-2N2P Logic Circuits", Proceedings of the 1995 International Workshop on Low-Power Design, 1995.
  13. W. C. Athas. et al, "A Low-Power Microprocessor Based on Resonant Energy", IEEE Journal of Solid-State Circuits, Vol.32, No.11, 1997.
  14. D. Maksimovic, et al, "Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply: Experimental Results", Proceedings of 1997 International Symposium on Low Power Electronics and Design, August 18-20, 1997, Monterey, California
  15. V. G. Oklobdzija, “Architectural Tradeoffs for Low Power”, International Symposium on Computer Architecture, Barcelona, SPAIN, June 27-July 1st, 1998.
 
Clock System and High-Performance Latches
  1. Eby G. Friedman, "Clock Distribution Networks in VLSI Circuits and Systems", in IEEE Press, 1995.
  2. Wagner, "Clock System Design", IEEE Design & Test of Computers, October 1988.
  3. S.H. Unger, C. Tan, "Clocking Schemes for High-Speed Digital Systems", IEEE Transactions on Computers, Vol C-35, No 10, October 1986.
  4. Minami, M. Takano, "Clock Tree Synthesis Based on RC Delay Balancing", Proceedings of IEEE Custom Integrated Circuits Conference, p. 28.3.1-28.3.4, May 1992.
  5. Kojima, S. Tanaka, K. Sasaki, "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry", IEEE Journal of Solid-State Circuits, Vol.30, No.4, April 1995.
  6. M. Afghahi, C. Svensson, "A Unified Single-Phase Clocking Scheme for VLSI Systems", IEEE Journal of Solid-State Circuits, Vol 25, No 1. February 1990.
  7. J. Yuan, et al, "New Single-Clock CMOS Latches and Flip-Flops with Improved Speed and Power Savings", IEEE Journal of Solid-State Circuits, Vol. 32, No.1, January, 1997.
  8. H. Partovi et al, "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements",Proceedings of 1996 IEEE International Solid-State Circutis Conference, San Francisco, California February 1996.
  9. D. Dobberpuhl et al, "A 200MHz 64-b Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, Vol 27, No 11. November 1992.
  10. B. J. Benschneider, et al, "A 300-MHz 64-b Quad-Issue CMOS RISC Microprocessor", IEEE Journal of Solid-State Circuits, Vol 30, No 11. November 1995.
  11. V.Stojanovic and V.G. Oklobdzija, "Comaparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power VLSI Systems," IEEE Journal of Solid-State Circuits, Vol.34, No.4, April 1999.
  12. B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. Chiu, M. Leung, " Improved Sense Amplifier-Based Flip-Flop: Design and Measurements", IEEE Journal of Solid-State Circuits, Vol. 35, No. 6, June 2000.


    High-Performance Arithmetic Units

  1. Weinberger, J.L. Smith, "A Logic for High-Speed Addition", National Bureau of Standards, Circulation 591, p. 3-12, 1958.
  2. Naini, D. Bearden, W. Anderson, "A 4.5nS 96-b CMOS Adder Design", IEEE 1992 Custom Integrated Circuits Conference, 1992.
  3. Sklanski, "Conditional-Sum Addition Logic", IRE Transaction on Electronic Computers, EC-9, pp. 226-231, 1960.
  4. V.G. Oklobdzija, E.R. Barnes, "Some Optimal Schemes for ALU Implementation in VLSI Technology", Proceedings of 7th Symposium on Computer Arithmetic, June 4-6, 1985, University of Illinois, Urbana, Illinois.
  5. B.D. Lee, V.G. Oklobdzija, "Improved CLA Scheme with Optimized Delay", Journal of VLSI Signal Processing, Vol. 3, p. 265-274, 1991.
  6. V. G. Oklobdzija, "An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis", IEEE Transactions on VLSI Systems, Vol. 2, No. 1, March 1994.
  7. C.S. Wallace, "A Suggestion for a Fast Multiplier", IEE Transactions on Electronic Computers, EC-13, p.14-17, 1964.
  8. L. Dadda, "Some Schemes for Parallel Multipliers", Alta Frequenza, Vol.34, p.349-356, March 1965.
  9. W. J. Stenzel, W. J. Kubitz, "A Compact High-Speed Parallel Multiplication Scheme", IEEE Transaction on Computers, C-26, p.948-957, 1977.
  10. V.G. Oklobdzija, D. Villeger, S. S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using and Alghoritmic Approach", IEEE Transaction on Computers, Vol.45, No.3, March 1996.
  11. V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers", in "Design of High-Performance Microprocessor Circuits", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.
  12. P. Stelling , V. G. Oklobdzija, “Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier”, special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol.14, No.3, December 1996.
  13. P. Stelling, C. Martel, V. G. Oklobdzija, R. Ravi, “Optimal Circuits for Parallel Multipliers,” IEEE Transaction on Computers, Vol. 47, No.3, pp. 273-285, March, 1998.