EEC 280: Advanced Logic Design

Fall 2001

Prof. Vojin G. Oklobdzija
Telephone: 752-5634
Office Hours: M 2-3pm, and by appointment via e-mail


Course Description:

This course addresses selected topics in logic design of complex and high-performance systems such as: advanced circuits technology for high-speed logic; low power ; clocking and timing of high performance systems; high-performance latch and pipelining; pipeline conflicts and hazard resolution; high-performance circuits for fast computer arithmetic and algorithms for fast computation; design methodology and use of hierarchy in the design. (detailed course description)


The course carry a project which may require the use of CAD tools (Cadence, H-Spice, Synopsys). It is possible to carry the project to implementation as an extension of this course (thesis project). The project is determined at the beginning of the course. The goal of this project is to provide a possible M.Sc. thesis to result in a publication, or provide a learning research experience.

This short course is divided into five sections of study. Outline is as follows:

I. Logic Design in New and Emerging Technologies:

A. Basic relations and analysis of CMOS

B. Differential Logic - Issues

C. New developments and directions in CMOS

D. Discussion and examples from advanced CMOS circuits.

II High-performance sub-micron CMOS circuits:

A. New Pass-Transistor Differential CMOS

B. High-Speed and Low Power CMOS

C. Examples from DPL and CPL.

III. Low-Power Logic:

A. General Principles

B. Principles of Adiabatic Logic

C. Clocking, gates and latch design

IV. Timing and Clocking:

A. Latch Design

B. Clock Distribution Generation

C. Methodology for Clocking and Clock Distribution: LSSD

D. Relations between the critical path and latch parameters

E. DEC Alpha clocking


V. Advanced Pipelining: VI. Arithmetic Algorithms and Technology Mapping:

Prerequisite: BSEE or coursework / experience in logic and circuit design 

Project : 50%

Exams: 50%