**EEC278: Computer Arithmetic**

Prof. Vojin G. Oklobdzija

Electrical and Computer
Engineering Department

University of California

Davis

**Content of the Course:**

This course consists of a set of lectures dealing with topics and issues in design of arithmetic units for high-performance and low power systems. Those issues covered in this course range from algorithms to VLSI implementation of various arithmetic structures.

The lecture starts with a set of papers
on number representation systems. They include fundamental papers on nuber
representation systems and it treats the use of redundancy in number
representation.

The next set of lectures is dedicated
to arithmetic operations such as: addition, multiplication, division and square
root. The speed of those operation
often determines the speed of a processor. The power consumed by the arithmetic
processor is becoming very important
in mobile and portable appliances and applications. Therefore we will treat the
issue of power consumed by those operations as well.

Next section deals with the floating-point
numbers and floating-point computation. It contains papers dealing with efficient
implementation of floating-point processor. The next set of papers deals with
the floating-point standard and issues that are relevant to it.

Evaluation of functions will also be addressed as well as techniques that achieve the functionality and high performance.

Thorough the course we will be dealing with VLSI algorithms and relationship between implementation techniques, choice of the appropriate algorithm and logic technology. The goal is to extract the benefits of both and achieve efficient and fast implementation. The section addresses the papers on fast and optimal implementation of ALU, parallel multiplier and MAC units that are a common building block of the Digital Signal Processing (DSP) systems. The presented work emphasizes the importance of appropriate algorithm and its proper mapping into the technology of choice.

This course is intended for a graduate
student in electrical and computer engineering, but it is also a reference for
the practicing engineer. It is intended to provide a useful and needed
reference to a collection of accumulated experience necessary for a good and
successful design.

List of papers covered in this course:

**High-Performance
Arithmetic Units**

- Weinberger, J.L. Smith,
*"A Logic for High-Speed Addition"*, National Bureau of Standards, Circulation 591, p. 3-12, 1958. - Naini, D. Bearden, W. Anderson,
*"A 4.5nS 96-b CMOS Adder Design"*, IEEE 1992 Custom Integrated Circuits Conference, 1992. - Sklanski, "Conditional-Sum Addition Logic", IRE Transaction on Electronic Computers, EC-9, pp. 226-231, 1960.
- V.G. Oklobdzija, E.R. Barnes,
*"Some Optimal Schemes for ALU Implementation in VLSI Technology"*, Proceedings of 7th Symposium on Computer Arithmetic, June 4-6, 1985, University of Illinois, Urbana, Illinois. - B.D. Lee, V.G. Oklobdzija,
*"Improved CLA Scheme with Optimized Delay"*, Journal of VLSI Signal Processing, Vol. 3, p. 265-274, 1991. - V. G. Oklobdzija,
*"An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis"*, IEEE Transactions on VLSI Systems, Vol. 2, No. 1, March 1994. - C.S. Wallace,
*"A Suggestion for a Fast Multiplier"*, IEE Transactions on Electronic Computers, EC-13, p.14-17, 1964. - L. Dadda,
*"Some Schemes for Parallel Multipliers"*, Alta Frequenza, Vol.34, p.349-356, March 1965. - W. J. Stenzel, W. J. Kubitz
*, "A Compact High-Speed Parallel Multiplication Scheme"*, IEEE Transaction on Computers, C-26, p.948-957, 1977. - V.G. Oklobdzija, D. Villeger, S. S. Liu,
*"A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using and Alghoritmic Approach"*, IEEE Transaction on Computers, Vol.45, No.3, March 1996. - V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and
Multipliers", in "
__Design of High-Performance Microprocessor Circuits__", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000. - P. Stelling , V. G. Oklobdzija, “Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier”, special issue on VLSI Arithmetic, Journal of VLSI Signal Processing, Kluwer Academic Publishers, Vol.14, No.3, December 1996.
- P. Stelling, C. Martel, V. G. Oklobdzija, R. Ravi, “Optimal Circuits for Parallel Multipliers,” IEEE Transaction on Computers, Vol. 47, No.3, pp. 273-285, March, 1998.