EEC272: High-Performance Computer Architecture: Super-Scalar Processor Design


Prof. Vojin G. Oklobdzija
Electrical and Computer Engineering Department
University of California


Content of the Course:

This course consists of lectures dealing with topics and issues in architecture and design of complex and high-performance computer systems. Those issues range from efficient instruction set design, pipelining, advanced pipelining and super-scalar computer implementation, exploitation of instruction level parallelism, memory hierarchy and multiprocessing. Thos issues are foundation of modern computer architecture and design.

The lecture will follow the textbook closely chapter by chapter. The schedule of lectures and what will be covered each week is given. In addition, I am planning on inviting a few visiting lectures by prominent computer designers or architects. The book will be enhanced by selected readings of some of the fundamental papers in computer architecture and design. The list of those papers is given bellow. In addition I recommend the excellent alternate book by Mike Johnson.

Students who want to carry an independent project that would lead to their MSc thesis or journal/conference paper are encouraged to do so. It will be graded on a different scale but it is not required.

This course is intended for a graduate student in electrical and computer engineering, as well as  for the practicing engineer. It is intended to provide a useful and needed reference to a collection of accumulated experience necessary for a good and successful design and understanding of complex computer systems today.

Topics covered and schedule:


Schedule of the Lectures

CMU Lectures ZIP file

Homework Assignments

(Homework's are due on Tuesday the following week)

Homework Solutions

Week 1: April 4, 6

Reading, Chpt. 1: Processor Design:

- The Evolution of Microprocessors -Instruction Set Processor Design

-Principles of Processor Performance

-Instruction-Level Parallel Processing

Homework 1:


Week 2:  April 11, 13

Reading, Chpt. 2: Pipelined Processors:

-Pipeline Design Fundamentals

-Pipelined Processor Design

-Deeply Pipelined Processors

-Encoding an Instruction Set

Homework 2:

2.1,2.2,  2.11- 2.15



Solutions to be handed in class

Week 3: April 18, 20

Reading: Chpt. 3: Superscalar Organization:

-Limitation of Scalar Pipelines

-From Scalar to Superscalar Pipelines

-Superscalar Pipeline Overview

Homework 3:




Week 4: April 25, 27  

Reading: Chpt. 4: Superscalar Techniques:

-Instruction Flow Techniques

-Register Data Flow Techniques

-Memory Data Flow Techniques

Homework 4:




Week 5: May 2, 4

Reading: Chpt. 7: Survey of Superscalar Processors:

-Development of Superscalar Processors

-A Classification of Recent Designs

Homework 5:

5.19 to 5.25 (due May 11)



Week 6: May 9, 11

Reading: Chpt. 7: Survey of Superscalar Processors:

Processor Descriptions:

  1. Compaq / DEC Alpha
  2. Hewlett-Packard PA-RISC

Homework 6:




Week 7: May 16, 18

Reading: Chpt. 6,7: Survey of Superscalar Processors:

Processor Descriptions:

  1. Intel i960
  2. Intel IA32
  3. MIPS
  4. Motorola 88220
  5. IBM Power

Homework 7:

6.2 - 6.9, 7.1 - 7.3 (due May 25)



Week 8: May 23-25

Reading: Chpt. 5,7: Survey of Superscalar Processors:

Processor Descriptions:

  1. IBM Power
  2. PowerPC: The PowerPC 620
  3. SPARC Version 8 &9

Homework 8:




Week 9: May 30, June 1

Reading: Chpt. 8: Executing Multiple Threads:

-Synchronizing Shared-Memory Threads

-Introduction to Multi-Processor Systems

-Explicitly Multithreaded Processors

-Implicitly Multithreaded Processors

-Executing the Same Thread

Homework 9:




Week 10: June 6, 8
Reading: Chpt. 9: Advanced Register Data Flow Techniques:

-Value Locality and Redundant Execution

-Exploiting Value Locality without Speculation

-Exploiting Value Locality with Speculation