EEC270: Computer Architecture

Prof. Vojin G. Oklobdzija
Electrical and Computer Engineering Department
University of California

 

Content of the Course:

This course consists of lectures dealing with topics and issues in architecture and design of complex and high-performance computer systems. Those issues range from efficient instruction set design, pipelining, advanced pipelining and super-scalar computer implementation, exploitation of instruction level parallelism, memory hierarchy and multiprocessing. Thos issues are foundation of modern computer architecture and design.

The lecture will follow the textbook closely chapter by chapter. The schedule of lectures and what will be covered each week is given. In addition, I am planning on inviting a few visiting lectures by prominent computer designers or architects. The book will be enhanced by selected readings of some of the fundamental papers in computer architecture and design. The list of those papers is given bellow.

The student in the course is requred to carry out an independent project of his/her choice. The purpose of this project is to introduce the student into research and allow in depth coverage of a particular problem related to computer architecture and design. The best of those projects could potentially result in published papers, which happened in the past. 

This course is intended for a graduate student in electrical and computer engineering, as well as  for the practicing engineer. It is intended to provide a useful and needed reference to a collection of accumulated experience necessary for a good and successful design and understanding of complex computer systems today.

 
Topics covered and schedule:

 

Schedule of the Lectures (you can download lecture overheads from Prof. Patterson's CS252 S99 web site)	Homework Assignments (Homework's are due on Monday's the following week)	Homework Solutions
Week 1: Jan. 7-11 Reading: Chpt. 1  Course overview, Fundamentals of Computer Design:  - Technology trends - Task of Computer Designer - Measuring Performance - Quantitative Principles of Computer Design	Homework 1: (due 14th) 1.1 - 1.7
Week 2: Jan. 14-18  Reading: Chpt. 2 Instruction Set Principles and Examples - Classifying Instruction Set Architecture: RISC vs CISC - Operations in the Instruction Set - Encoding an Instruction - The Role of Compiler	Homework 2: (due 25th) 2.1 - 2.5
Week 3: Jan. (21*)-25  *Holiday Reading: Chpt. 2: Instruction Set Principles and Examples - Addressing - Historical Perspective - Fallacies and Pitfals	Homework 3: (due 28) 2.11, 2.12, 2.17
Week 4: Jan. 28-Feb.1   Reading: Chpt. 3: Pipelining: - General Principles -The Basic Pipeline - Pipeline Hazards:   - Instruction Set Design and Pipelining - Performance and Pipelining	Homework 4: (due Feb 4th) 3.1 - 3.5
Week 5: Feb.4-8 (ISSCC) Reading: Chpt. 4: Advanced Pipelining and Instruction-Level Parallelism: - Instruction-Level Parallelism - Dynamic Scheduling	Homework 5: (due 11th) 4.1 - 4.5
Week 6: Feb. 11-15 Reading: Chpt. 4:  Advanced Pipelining and Instruction-Level Parallelism: -  Reducing Branch Penalties: Dynamic Branch Prediction - Multiple Issue: Taking advantage of ILP - Compiler Support in Exploiting ILP - Hardware Support for Extracting More Parallelism - Historical Perspective	Homework 6: (due 22nd) 4.7 - 4.10
Week 7: Feb. (18*)-22   *Holiday Reading: Chpt. 5:  Memory Hierarchy Design: - Cache Principles and Design - Reducing Cache Misses and Miss Penalty	Homework 7: (due 25th) 5.4 - 5.7
Week 8: Feb. 25-March 1. Reading: Chpt. 5:  Memory Hierarchy Design - Main Memory - Virtual Memory -  Protection and Examples of Virtual Memory -  Example: Alpha AXP 21064 Memory Hierarchy	Homework 8: (due 4th) 5.8, 5.10
Week 9: March 4-8   Reading: Chpt. 8  Multiprocessing: -  Application Domains -  Centralized Shared-Memory Architectures -  Distributed Shared-Memory Architectures -  Synchronization -  Memory Consistency Models -  Crosscutting Issues	Homework 9: (due 11th) 8.1 - 8.7
Week 10: March 11-(15*) *Monday class  Project Presentations, Final Exam

 

 

List of recommended readings:
 

[1] C.J. Bashe et al., "The Architecture of IBM's Early Computers", IBM Journal of Research and Development, 25:5 (Sep 1981), p.363-375.

[2] John Voelcker, "The PDP-8", IEEE Spectrum 25th Anniversary, p.86-92.

[3] G.A. Blaauw and F.P. Brooks, "The Structure of System/360", IBM Sysetms Journal, 3:2 (1964), p.119-135.

[4] A. Padegs, "System/360 and Beyond", IBM Journal of Research and Development, 25:5 (Sep 1981), p.377-390.

[5] C.G. Bell et al., "The IBM System/360, System/370, 3030, and 4300: A Series of Planned Machines that Span a Wide Performance Range", p.856-892.

[6] W.D. Strecker, "VAX-11/780 - A Virtual Address Extension to the DEC PDP-11 Family", AFIPS Proceedings NCC, (1978), p.767-980.

[7] James E. Thornton, "Parllel Operation in the Control Data 6600", AFIPS Proceedings FJCC part 2, vol 26 (1964), p.33-40.

[8] D.W. Anderson et al., "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling", IBM Journal, vol 11 (Jan 1967), p.8-24.

[9] Johnny K.F. Lee and A.J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", Computer, 17:1 (1984), p.6-22.

[10] Wen-mei W. Hwu et al., "Comparing Software and Hardware Schemes for Reducing the Cost of Branches".

[11] R.E. Matick and D.T. Ling, "Architecture Implications in the Designof Microprocessors", IBM Systems Journal, 23:3 (1984), p.264-280.

[12] A.J. Smith, "Cache Memory Design: An Evolving Art", IEEE Spectrum, (Dec 1987), p.40-44.

[13] Computer Architecture and Parallel Processing, sec 2.4 - Cache Memories and Management.

[14] A.J. Smith, "CPU Cache Memories", (Apr 1984), updated version of ACM Surveys, 14:3 (Sep 1982), p.473-530.

[15] A.J. Smith, "Line (Block) Size Choice for CPU Cache Memories", IEEE Transactions on Computers, C-36:9 (Sep 1987), p.1063-1075.

[16] A.J. Smith, "Cache Evaluation and the Impact of Workload Choice", Proceedings of 12th Annual International Symposium on Computer Architecture, (Jun 17-19 1985), p.64-73.

[17] J.S. Lipton, "Structural Aspects of the System/360 Model 85 - II The Cache", IBM Systems Journal, 7:1 (1968), p.5-21.

[18] L.A. Belady, "A Study of Replacement Algorithms for a Virtual-Storage Computer", IBM Systems Journal, 5:2 (Nov 1966), p.78-101.

[19] Mark S. Papamarcos and Janak H. Patel, "A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories", Proceedings of 11th Annual Symposium on Computer Architecture, Ann Arbor MI (5-7 Jun 1984), p.348-354.

[20] James Archibald and Jean-Loup Baer, "An Economical Solution to the Cache Coherence Problem", (1984), p.355-362.

[21] Peter J. Denning, "Virtual Memory", Computing Surveys, 2:3 (Sep 1970),
 p.153-189.

[22] Peter J. Denning, "The Working Set Model for Program Behavior", Communications of ACM, 11:5 (May 1968), p.323-332.

[23] Shreekant S. Thakkar and Alan E. Knowles, "A High-Performance Memory Management Scheme", Computer, 19:5 (May 1986), p.8-20.

[24] Douglas W. Clark and Joel S. Emer, "Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement", ACM Transactions on Computing Systems, 3:1 (Feb 1985), p.31-62.

[25] Albert Chang and Mark F. Mergen, "801 Storage: Architecture and Programming", ACM Transactions on Computing Systems, 6:1 (Feb 1988), p.28-30.

[26] C.V. Ramamourthy, "Pipeline Architecture", Computing Surveys, 9:1 (Mar 1977), p.61-101.

[27] R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, vol 11 (Jan 1967), p.25-33.

[28] Gerry Kane, "MIPS RISC Architecture", Chapter 1 - RISC Architecture: An Overview, 1989.

[29] George Radin, "The 801 Minicomputer", IBM Research Report, RC 9125 (#39926) 11/11/81.

[30] Gregory J. Chaitin et al., "Register Allocation via Coloring", IBM Research Report RC 8395 (#36543) 8/4/80.

[31] David A. Patterson and Carlo H. Sequin, "A VLSI RISC", Computer, 15:9 (Sep 1982), p.8-21.

[32] David A. Patterson and Carlo H. Sequin, "RISC I: A Reduced Instruction Set VLSI Computer", Proceedings of 8th Annual Symposium on Computer Architecture, Minneapolis MN (Aug 1981), p.443-457.

[33] Robert G. Sherburne Jr. et al., "Local Memory in RISCS", Proceedings of IEEE International Conference on Computer Design: VLSI in Computers (ICCD 1983), Port Chester NY, (31 Oct-3 Nov 1983), p.149-152.

[34] John L. Hennessy, "VLSI Processor Architecture", IEEE Transactions
 on Computers, C-33:12 (Dec 1984), p.1221-1246.

[35] John Hennessy et al., "Performance Issues in VLSI Processor Design", (1983), p.153-156.

[36] Gerry Kane, "MIPS RISC Architecture", chapters 2-5, Prentice-Hall, 1989.

[37] Carl Dobbs et al., "Supercomputing on Chip", VLSI System Design, (May 1988), p.24-33.