EEC180B                 DIGITAL SYSTEMS II             Fall 1999

Reading Assignments

                    Instructor: Prof. Vojin G. Oklobdzija

Course Overview and Tentative Schedule (reading assignments)

Textbooks:
  1. Charles H. Roth, "Fundamentals of Logic Design", West Publishing Company
  2. *D. Patterson, J. Hennessy, "Computer Organization and Design: The Hardware/Software Interface", Morgan Kaufmann Publishers.
Schedule of the Lectures
Schedule of the Labs
Week 0: (Sept. 30)  No Labs
Week 1: (Oct. 5-7) 

Reading: Chpt. 6, 8, 9, 10, 11, A1-4

Course overview, Review of the laboratory assignment and project

Lab 1:

Introduction into Altera design tools.
Memory interfacing.

Week 2: (Oct 12, 14)

Reading: Chpt. 6, 8, 9, 10, 11, 26, A1-4

Review of the Logic Design (180A): 

Karnaugh Maps, Multi-level Gate Networks, Flip-Flops, Hazards

Lab 2:

Register File Design

Week 3: (Oct 19, 21) 

Reading: Chpt . 10, 11, 12, 13, 14, 15, 16

Review of the Logic Design (180A): 

Counters and Sequential Networks, FSM design, FSM diagram and representations.

Examples.

Lab 3:
 
 

Finite State Machine Design

Week 4: (Oct 26, 28) 

Reading: Chpt. 17, 20

Iterative Networks, Networks for Addition/Subtraction.

Lab 4:

Controller Design

Week 5: (Nov 2, 4)

Reading: Chpt. 4*, 20

Computer Arithmetic: ALU design, Multiplication.

Lab 5:

Fast ALU Design

Week 6: (Nov 9, 11) 

Reading: Chpt. 3*, 18

Basic Computer Organization, Computer Instructions- interface with the control logic, MSI Integrated Circuits.

Lab 6:

Fast ALU Design

Week 7: (Nov 16, 18) 

Reading: Chpt. 19, 5*

Sequential Network Design - FSM Using PLAs and PLDs, Microprogramming:

Lab 7:

Microprocessor Design - MISP

Week 8: (Nov 23, 25)

Reading: Chpt. 5*, 22, 23, C

Design of ControlUnit, Various design styles. Mapping Control to Hardware

Lab 8:

Microprocessor Design - MISP

Week 9: (Nov 30, Dec 2)

Reading: Chpt. 24, 25, 

Derivation and Reduction of Primitive Flow-Tables, State Assignment and Realization of Flow-Tables.

Lab 9:

Microprocessor Design - MISP

Week 10: (Dec 7, 9) 

Reading: Chpt. 6*

Enhancing performance with pipelining.

Lab 10:

Microprocessor Design - MISP