EEC180A DIGITAL SYSTEMS I Winter 2006
Instructor: Prof. Vojin
G. Oklobdzija ( Voi-n O-klob-j-i-a)
Office: Kemper Hall, Room 3007, Phone: 752-5634
Office Hours: M,W 4-5pm, Kemper Hall, Room 2221 and by appointment via e-mail.
E-mail: vojin@ece.ucdavis.edu
Course Grading:
HOMEWORKS
.......................................10%
MIDTERM ..............................................30%
LABORATORY .......................................20%
FINAL EXAM ..........................................40%
Scheduling: Holidays: Monday January 16th (class will meet on January 20th instead) and February 20th.
Course Text: Charles H. Roth Jr., Fundamentals of Logic Design, 5th Edition, Thomson Brooks Cole.(ISBN: 0534378048) Book Website
Additional References: (Physical Sciences Library):
R. Katz Contemporary Logic Design, The Benjamin/Cummings Publishing Company Inc., 1994.
M.Ercegovac, T.Lang Digital Systems and Hardware /Rirmware Algorithms, John Wiley & Sons, 1985
McCluskey, E. J. Logic Design Principles, Prentice-Hall, 1986.
Sandige, R. S. Modern Digital Design, McGraw-Hill, 1990.
Hill, F. J. and Computer Aided Logical Design with Emphasis on VLSI
Peterson, G. R. (Fourth Edition) John Wiley&Sons, 1993.
Mano, M. M. Digital Design (Second Edition), Prentice-Hall, 1991.
Texas Instruments, Inc. The TTL Data Book for Design Engineers (Second Edition), 1981.
EEC180A DIGITAL SYSTEMS I Winter 2006
ORDERED TOPICS AND PERTINENT TEXT SECTIONS
Charles H. Roth, Fundamentals of Logic Design, West Publishing Company
|
Topics |
Text Sections |
|
Number Systems and Representations |
1.1 - 1.2, 1.4-1.5 |
|
Arithmetic Operations |
1.3 -1.4 |
|
Boolean Algebra |
2.1 - 2.8, 3.1 - 3.2 |
|
Algebraic Simplification |
3.3 - 3.5 |
|
Applications of Boolean Algebra |
4.1 - 4.6 |
|
Karnaugh Maps |
5.1 - 5.4, 5.6 - 5.7 |
|
Multi-Level Gate Circuits |
7.1 - 7.7 |
| Combinational Circuit Design | 8.1 - 8.5 |
|
Multiplexers, Decoders, ROM and PLA |
9.1 - 9.7 |
|
Latches and Flip-Flops |
11.1 - 11.9 |
|
Registers and Counters |
12.1 - 12.6 |
|
Analysis of Clocked Sequential Networks |
13.1 - 13.4 |
|
Derivation of State Graphs and Tables |
14.1 - 14.5 |
|
Reduction of State Tables, State Assignment |
15.1 - 15.9 |
|
Sequential Circuit Design |
16.1 - 16.3 |
|
Sequential Circuit Design using PLDs |
16.4 - 16.6 |
|
Circuits for Arithmetic Operation |
4.7, 18.1-18.3 |