EEC180A
DIGITAL SYSTEMS
I
Spring 2000
Instructor: Prof. Vojin G. Oklobdzija ( Voi-n
O-klob-j-i-a)
Office: 3007 EU-II, Phone: 752-5634
Office Hours: TBA and by appointment and via e-mail.
E-mail: vojin@ece.ucdavis.edu
Course Grading:
HOMEWORKS .......................................10%
QUIZZES ..................................................25%
MIDTERM ..............................................20%
LABORATORY .......................................20%
FINAL EXAM ..........................................25%
Scheduling: Holidays: TBA
Course Text: Charles J. Roth, Fundamentals of Logic Design, West Publishing Co., 1993.
Additional books could be checked at the
Physical Sciences Library.
Additional References: (Physical Sciences Library):
R. Katz Contemporary Logic Design, The Benjamin/Cummings Publishing Company Inc., 1994.
M.Ercegovac, T.Lang Digital Systems and Hardware /Rirmware Algorithms, John Wiley & Sons, 1985
McCluskey, E. J. Logic Design Principles, Prentice-Hall, 1986.
Sandige, R. S. Modern Digital Design, McGraw-Hill, 1990.
Hill, F. J. and Computer Aided Logical Design with Emphasis on VLSI
Peterson, G. R. (Fourth Edition) John Wiley&Sons, 1993.
Mano, M. M. Digital Design (Second Edition), Prentice-Hall, 1991.
Texas Instruments, Inc. The TTL Data Book for Design Engineers (Second Edition), 1981.
EEC180A DIGITAL SYSTEMS I Spring 2000
ORDERED TOPICS AND PERTINENT TEXT SECTIONS
Charles H. Roth, Fundamentals of Logic Design, West Publishing Company
|
Topics |
Text Sections |
|
Number Systems and Representations |
1.1 - 1.2 |
|
Arithmetic Operations |
1.3 |
|
Boolean Switching Algebra |
2.1 - 2.7 |
|
Boolean Switching Algebra |
3.1 - 3.5 |
|
Algebraic Simplification |
4.1 - 4.3 |
|
Applications of Boolean Algebra |
5.1 - 5.6 |
|
Karnaugh Maps |
6.1 - 6.4, 6.6-6.7 |
|
Multi-Level Gate Networks |
8.1 - 8.7 |
|
Multiplexers, Decoders, ROM and PLA |
9.1 - 9.7 |
|
Combinational Network Design |
10.1 - 10.3 |
|
Flip-Flops |
11.1 - 11.9 |
|
Counters and Sequential Networks |
12.1 - 12.9 |
|
Analysis of Clocked Sequential Networks |
13.1 - 13.4 |
|
Derivation of State Graphs and Tables |
14.1-14.4 |
|
Reduction of State Tables, State Assignment |
15.1-15.8 |
|
Sequential Network Design |
16.1 - 16.4 |
|
MSI Integrated Circuits in Sequential Network Design |
18.1 - 18.4 |
|
Sequential Network Design with PLDs |
19.1 - 19.4 |
|
Networks for Addition and Subtraction |
20.1 - 20.3 |
|
Hazards |
26.1 - 26.4 |