EEC180A                DIGITAL SYSTEMS I              Fall 2002
  Reading Assignments

Instructor: Prof. Vojin G. Oklobdzija

Office: 3007 EU-II, Phone: 752-5634
Office Hours M 4-5pm, and by appointment via e-mail.

E-mail: vojin@ece.ucdavis.edu



 

NOTE: Homework assignments are collected the Friday of the week they are assigned!! (at Midnight)

Your reader is: Brendan Lee he is available Wednesday 6:30-7:00 in 2110 to answer your question. It is preferred that you contact him via e-mail



Course Overview and Tentative Schedule* (reading assignments)

*The schedule presented here is tentative. Actual schedule will depend on the level and background of the particular class. There is no guarantee that this schedule will be followed exactly. However, you are still responsible for all the labs and assignments.

Schedule of the Lectures

Schedule of the Labs

Homework Assignments

Week 1: Sep. 30-Oct. 6

Reading: Chpt. 1 
Course overview, The Process of Design, Digital Hardware Systems: 
- review of logic design, nuber systems and number representation, arithmetic operations with binary numbers.

No Labs

Homework 1:

Chpt.1, Probl: 1.1-1.10

Hwk1-Solutions

Week 2: Oct. 7-13 

Reading: Chpt. 2, 3 Appendix A
Boolean Switching Algebra
- Boolean Algebra, introduction, basic theorems
- Expressions, laws, positive and negative logic

Lab 1:

Intorduction to lab instruments and work environment

Homework 2:

Chpt.2, 3, Probl: 2.1-2.6 and 3.3-3.9
 Probl:  A1-A5 (appendix)  due Monday October 14, 2002

Hwk2-Solutions

Appendix-A-Solutions

 

Week 3: Oct. 14-20

Reading: Chpt . 4, 5 
Boolean Algebra:
- Algebrtaic Simplifications 
- Applications of Boolean Algebra 
- Minterm and Maxterm expansions 
- Gate Logic, Implementations

Lab 2:

Introduction to Computer Aided Design: 
Altera design system: tutorial

Homework 3:

Chpt.4,5, Probl: 4.4-8, 5.1, 5.2, 5.9, 5.21-24.

Week 4: Oct. 21-27  last day to drop  

Reading: Chpt. 6, 8 
Minimization Tools:
- Karnaugh Maps 
- Multi-level Gate Networks 
- Implementation wiht NAND and NOR gates

Lab 3:

Combinational Network Design using Algebraic Simplifications

Homework 4:

Chpt. 6,8, Probl: 6.5-6.12, 8.1-8.7.

Week 5: Oct. 28-Nov. 3

Reading: Chpt. 9, 10
MSI, Programmable and Non-Gate Logic
- Multiplexers, Decoders 
- ROM and PLA (PAL) 
- Design of combinational networks

Lab 4:

Combinational Network Design using Karnaugh Maps

Homework 5:

Chpt. 9, 10, Probl: 9.1-5, 9.20-21, 10.1-4, 10.14.

Week 6: Nov. 4-10

Reading: Chpt. 11,12 
Memory Elements, use of Memory Elements in the design:
- Flip-Flop Circuit: D, R-S, J-K, T 
- Clocking, Edged Triggered, Level Sensitive 
- Master-Slave Latch 
- Timing and Clock Distribution 
- Counters and sequential networks

Lab 5:

Combinational Network Design using Multiplexers and PALs

Homework 6:

Chpt. 11,12, Probl: 11.3-6, 11.13, 12.1-4, 12.14-15.

Week 7: Nov. 11*-17 *(holiday)

Reading: Chpt. 13, 14 
Sequential Logic Design
- Analysis of Clocked Sequential Networks 
- State Graphs and Tables 
- Derivation of State Graphs and Tables 
- Different FF realizations 
- Examples

Lab 6:

Flip--Flops and Latches

Homework 7:

Chpt. 13, 14, Probl: 13.2-5, 14.13-16.

Week 8: Nov. 18-24

Reading: Chpt. 15, 16 

Sequential Networks Design
- Reduction of State Tables 
- State Assignment 
- Guidelines for State Assignment 
- Practical examples

Lab 7:

Design of Counters

Homework 8:

Chpt. 15, 16, Probl: 15.1-5, 16.1-2.

Week 9: Nov. 25-Dec 1  

Reading: Chpt. 18, 19 
Sequential Logic using MSI and PLDs
- Registers and Counters 
- Design using Counters 
- Register Transfer and 3-state Logic 
- Finite State Machine Design using ROMs and PLAs and PALs 
- Programmable Gate Arrays: PGAs and FPGAs

Lab 8:

Sequential Network Design

Homework 9:

Chpt. 18, 19, Probl: 18.2, 18.5-6, 18.8, 19.1, 19.7.

Week 10: Dec. 2-8 

Reading: Chpt. 20 
Arithmetic Circuits
- Networks for Addition/Subtraction 
- Binary Adders: RCA, CLA 
- Multiplication / Division 
- ALU Design

Lab 9:

Arithmetic Circuits

Homework 10:

Chpt. 20, Probl: 20.9-12.

   


It is in the student's best interest to do all the homework assignments and problems in the textbook. This increases the studentí's skills and enhances his/her abilities to solve problems. This is an essential part of this course, since in your future job this is what you will be doing. We will be collecting your homework the Friday of the week it is assigned at Midnight in the EEC180A homework box in 2131 EUII. Solutions will be posted to the website by the following Monday, so that you can check your work.