Electronic Circuits
EEC110A - Spring 2010
CRN: 61535
Mondays & Wednesdays 10:00-11:50 in 1062 Bainer
Announcements:
The final course grades are now available. The final exam solutions are here.
Prof. Spencer will hold special pre-exam office hours on Friday, June 4, from 12-2:30PM. Travis will hold office hours from 10-12 on Friday, June 4 (instead of his regular Friday office hours).
Some practice problems for the final are available here (note that this is a collection of old exam problems, not a single final exam), and the formula sheet that will be provided on the exam is available here.
Here are the slides I used in class on Monday, 5/24.
The solutions to the second midterm are available here, and your final midterm grades are here (the overall midterm is now worth 100 points, rather than 75, because I just used the best percentage. It will still count for the same fraction of your overall course grade though). I do not assign letter grades to individual assignments, but I would say, roughly, that if you got less than 33% on the midterm, you failed the exam.
As promised in class, here are the solutions to some more problems (P10.14, P10.88 & 10.92) to help you study for the midterm.
The LTI system appendix that I mentioned in class is available here.
The grades for the course up through the midterm are now available here. Let Professor Spencer know if you think there is some error.
The midterm solutions are available here.
Here is the midterm formula sheet to use for studying. This information will be provided on the examination itself. The test will be closed-book, closed-note, no calculators allowed.
Here is a practice midterm (it is missing a few problems that don't apply now that we have changed the class, so the full midterm was a bit longer).
Instructor
Prof. Richard Spencer, 2041 Kemper Hall, 752-6885
Please do not use email to contact me unless it is necessary (i.e., don’t use it in place of questions in class, the discussion session and office hours). My email address is: spencer@ece.ucdavis.edu
Office hours: Wednesdays, 1:00-3:00 in 2041 Kemper Hall
Prof. Spencer is also available after class every day and by appointment.
TA
Travis Kleeburg (email: tklee@ucdavis.edu)
Office hours: Fridays, 1:00-3:00 in 2101 Kemper Hall
Required Text
R. Spencer and M. Ghausi, Introduction to Electronic Circuit Design, Prentice Hall, 2003 Be sure to look at the book errata on the website: www.prenhall.com/spencer
Syllabus
Download a complete course syllabus here.
Webcasts of Lectures
You may view the Webcasts of the lectures here. You will need your UC Davis Login ID and Kerberos password.
If you have any questions about the webcasts, you may contact Jan Neff, the Program Coordinator for the Distance Learning Program. Her phone number is 530-752-2850 and her email address is jneff@ucdavis.edu.
Class Schedule
Date | Day | Topic | Reading[1] | Homework |
March 29 | M | Introduction. The design process. Analysis for design. | Chap. 1 | HW1 - Due Friday 4/2 by 5:00 - P1.7, P1.14, P1.30, P6.6, P6.10 |
31 | W | Small-signal approximation and analysis. Review two-port models. Amplifier models. DC bias models (large-signal DC models) and analyses for BJTs. | Chap. 6, Chap. 7 up through §7.1.4, and §7.2.1 | |
April 5 | M | Finish BJT biasing. Low-frequency small-signal (LFSS) BJT model. | Chap. 8 up through §8.1.5 | HW2 - Due Friday, 4/9 by 5:00 - P6.18, P7.5, P7.9, P7.16, P8.3, P8.36 |
7 | W | Finish LFSS BJT model. Start LFSS circuit analysis. | §8.2.1-8.2.2 | |
12 | M | LFSS circuit analysis – gain (CE) stage. | HW3 - Due Friday, 4/16 by 5:00 - P8.28, P8.30, P8.32 (this is a challenging design problem, so it will count as much as 3 normal HW problems. See page 356 in the text for a table of standard resistor values.) | |
14 | W | Finish CE stage. CC stage (emitter follower). | §8.3.1-8.3.2, §8.4.1-8.4.2 | |
19 | M | High-frequency small-signal (HFSS) diode and transistor models including b(jw) and fT.. | Chap. 9 up through §9.1.5 | HW4 - Due Friday, 4/23 by 5:00 - P8.121, P9.27 - add the following part (e): When R'i = 10 kW and A = 1.1, what is Ri?, P9.40 - add the following part (c): Assume RE is bypassed by a large capacitor. Find wCH assuming that rb = 50W, tF = 400ps, Cje0 = 10pF, Cjc0 = 5pF, Vo = 0.75V and m = 0.33. |
21 | W | Miller effect and approximate bandwidth of the CE stage. | §9.2.1-9.2.2 (“Introductory Treatment” only!) | |
26 | M | Bandwidth of emitter follower and CB stage (used in a cascode). Begin Negative Feedback (NFB): basic concept. | §9.3.1-9.3.2, §9.4.1-9.4.2, §9.6.1-9.6.2, §9.6.4-9.6.5 (“Introductory Treatment” only!) | HW5 - Due Friday, 4/30 by 5:00 - P9.124, P9.144 (keep a copy of your HW when you hand it in so you have something to study from) |
28 | W | NFB: advantages and characteristics. Ideal analysis, classification. | §10.1-10.1.2 (The material on noise and feedback is optional. You may also want to review Asides A1.1 and §6.5.1) | |
May 3 | M | Midterm (covers material up through lecture on 4/26) | HW6 - Due Friday, 5/7 by 5:00 - P10.4, P10.9, P10.11 | |
5 | W | NFB: Practical analysis, series-shunt. | §10.1.3 (up to the Series-Series Connection on page 698) | |
10 | M | NFB: Practical analysis, transistor-level series-shunt. | HW7 - Due Friday, 5/14 by 5:00 - P10.16, P10.53 (these will both count as two HW problems) | |
12 | W | NFB: Practical analysis, other connections. Begin loop gain and stability. | §10.1.3 (from page 698 on), §10.1.5 | |
17 | M | NFB: Finish loop gain and stability, gain and phase margins. Compensation | §10.1.6 | |
19 | W | Start Digital material: Introduction to digital circuits, Boolean algebra, binary logic gates. Second Midterm (see note at top) | Chap. 14 Introduction & §14.1; | |
24 | M | MOS device models for digital circuits. Inverter specifications & power dissipation. | Chap. 15 Introduction & §15.1.3 | HW8 - Due Friday, 5/28 by 5:00 - P14.2, P14.14, P14.17, P15.12, P15.14 |
26 | W | MOS inverter design. Start CMOS logic gates; NOR and NAND | §15.2-15.3.5 | HW9 - Due Wednesday, 6/2 by 5:00 - P15.23, P15.24, P15.28, P15.32, P15.33, P15.35 |
31 | M | Memorial Day Holiday | ||
June 2 | W | Complex CMOS gates. Course review | ||
7 | M | 8:00-10:00 AM Final Exam (Comprehensive - but will emphasize material since the midterm) |
[1] All reading assignments refer to the required text and should be completed before the lecture they are listed next to (except for the first lecture of course).
Homework Solutions:
Even when a link appears for a particular solution, the solution will not be available until after the time it is due. The username and password you need to read these files are on the course syllabus.
To access any file with the
icon, you will need to use Acrobat Reader.
If you do not have a copy of the Reader, you can download it from Adobe:
Revision history:(Only significant changes are noted - I don't note every time I add a homework assignment or announcement for example)
3/18/2010 The room changed and I added the TA.
3/30/2010 I added the webcast section.
5/4/2010 I changed the lecture schedule to reflect the fact that we are about one lecture ahead.
5/25/2010 I changed the lecture schedule to agree with our progress and to show that Monday, 5/31 is a holiday.
Webpage created on 2/3/10 by Richard Spencer
Last modified on: 5/25/10