University of
California, Davis
Department of
Electrical and Computer Engineering
EEC 180B – Digital
Systems II
Spring 2006
- Class announcements
- (5/31) Monday quiz will cover both hw #9 and #10.
- (5/31) HW #10:
problems 10.1, 10.3, 10.4, 10. 7, 10.10.
- (5/24) There will be no quiz on Wednesday 5/31. We will have the last quiz on Monday 6/5.
- (5/24) Additional office hours: Wedneday 5/31 2:30-4pm.
- (5/24) HW #9:
problems 9.1, 9.4, 9.5, 9.9, 9.12
- (5/24) Due
to time constraints, lab 6 is canceled and due date for lab 5 is
pushed back to the last week of the quarter. No further extensions will
be given. The reports for lab 5 are due right before the final exam on
6/13 at 8am.
- (5/24) Just
a quick reminder that Wednesday 5/31 is an academic Monday => the
Monday lab section will meet on 5/31 to makeup for the memorial day
holiday.
- (5/18) The quiz on wednesday (5/24) will cover hw #7 and #8.
- (5/18) HW #8:
problems 7.2, 7.4, 7.6, 7.7, 7.10
- (5/18) HW #7:
problems 6.1, 6.2, 6.6, 6.11, 6.15, 6.16
- (5/3) We will have
midterm review and problem discussion on Monday May 8th.
- (5/3) Midterm is
going to be on Wednesday May 10th. The test is open book/notes
and will cover chapters 1-5 and 8.
- (5/3) HW #6:
problems 5.1, 5.4, 5.6, 5.7, 5.8
- (4/24) There will be
no class on Wednesday 4/26.
- (4/24) HW#5:
problems 4.1, 4.2, 4.5, 4.8, 4.12
- (4/20) The
instructor's office hours are shifted to Mondays 2:30-4pm.
- (4/20) HW #4:
problems 3.1, 3.3, 3.4, 3.5, 3.9, 3.11.
- (4/12) HW #3:
problems 8.1, 8.5, 8.6, 8.9, 8.10.
- (4/6) Quiz and hw
solutions will
be posted here.
- (4/5) HW #2:
problems 2.3, 2.4, 2.8, 2.11, 2.14, 2.15
- (4/2) Lab
assignments and schedule are posted online.
- (3/29) HW #1:
review of 180A material (chapter 1 of your Roth text). This means that we
will have a quiz based on this homework on Wednesday 4/5.
- (3/29) Class
announcements will be posted here. Remember to hit the reload button to
see the updated version.
- Time and location
- Lectures:
MW 5:10-6:30pm, MW @194 Young
- Labs:
M, Tu, Th 7:10-11pm, Kemper 2107 (Open on Saturdays)
- Teaching Staff
- Instructor:
Soheil Ghiasi
- 3171
Kemper Hall
- Office
Hours: Monday 2:30-4pm
- Lab
TA's
- Robin
Lin (rhlin at ucdavis)
- Mandeep
Singh (mdsingh at ucdavis)
- Robert
Heath (rdheath at ucdavis)
- Reader
- Adam Harbour (adharbour at ucdavis)
- Communication
- Text Books
- "Digital
Systems Design Using VHDL" by Charles H. Roth (ISBN: 0-534-95099-X).
Major text used for lectures. You can download the text's errata and slides
- "Rapid
Prototyping of Digital Systems: A Tutorial Approach", by J.O.
Hamblen and M.D. Furman (ISBN: 0792374398), Second Edition, Kluwer
Academic Publishers, 2001. Required for some of the lab assignments.
- Grading Policy
- Lab
work %30
- Quizzes
%16
- Midterm
exam %21.6 (Wednesday, May 10 5-7pm)
- Final Exam %32.4 (Tuesday,
June 13 8:00-10:30 am)
- Additional Course Information
- Prerequisites:
EEC 70 or ECS 50; EEC 100 and EEC180A.
- All quizzes and exams cover material from assigned
readings, lectures, homework, and labs. Some material may be present in
only one of these sources.
- Course Policy
- Homework
- Howework
will be assigned on a weekly basis, but they will not be collected.
Solutions will be posted a few days after assignment and a few
days before weekly quiz.
- There
will be eight quizzes based on assigned homework problems.
- Labs
- Each
lab has three major components: 1) the prelab, 2) the
simulation/implementation work done in the lab, and 3) the lab report.
The first two components must be signed off by the TA, and your report
must be turned in to him/her. You may go to another section and use the
equipment only if there is space available. The students for that
section have priority for the equipment and assistance from the TA.
- Except
for Lab 1, prelabs are due at the beginning of the indicated lab
section. Lab checkoffs and lab reports are due at the beginning of the
lab section the following week immediately after prelab checkoffs.
Written work may be done on any type of paper (though graph paper will
generally produce a better result) and must be neat whether typed or
hand-written.
- Quizzes,
Midterm, and Final exam
- Eight
quizzes will be given throughout the course. Quiz problem will be
designed based on assigned homework problems such that students that
listen in lecture, do required readings and solve the homework
problems will earn very high scores.
- The
midterm and final exam are mandatory components of this course.
Unfortunately, no early or late exams are possible. If an unavoidable
emergency prevents your attendance at the midterm or final, you will be
required to submit written proof of the emergency and the make-up exam
will likely be given as an oral exam with the instructor.
- Final
exam will be cumulative but with an emphasis on material since the
midterm.
- Individual
work and Dishonesty
- In this course, all work must be done
"individually"--meaning done entirely by the student whose
name is on the work. However, asking other students conceptual questions
and explaining high-level concepts are important steps in the learning process
and are strongly encouraged. This is very different from giving or
receiving aid related to a specific assigned problem--which is not
permitted. Copying someone else's work or allowing your work to be
copied in any setting (lab, quizi, exams, etc) does not promote
learning, is unfair to honest students, and WILL BE immediately reported
to Student Judicial Affairs. Students that observe inappropriate
activity should report what they see (anonymously if desired) to a TA or
the instructor.
- Syllabus
- Review
of logic design fundamentals (180A review)
- combinational
logic design and optimization
- sequential
logic design and optimization
- Introduction
to VHDL
- signals,
variables, constants
- concurrent
vs. sequential modeling
- timing
- compilation
and simulation
- functions
and prodecures
- modeling
combinational and sequential designs
- synthesis
- Attributes
- multi-valued
logic and signal resolution
- generic
statements
- synthesis
- File
and TEXTIO
- Programmable
Logic Devices (PLDs)
- architecture
- design
implementation using programmable substrate
- automated
design
- Design
of Arithmetic Units
- signed
vs. unsigned operations
- integer
arithmetic
- adders
- multipliers
- dividers
- floating
point arithmetic
- adders
- multipliers
- other
operations
- Field
Programmable Gate Arrays (FPGA)
- architecture
- designing
with FPGAs
- state
assignment and technology mapping optimization for FPGAs
- complex
programmable logic devices
- Memory
and Bus models in VHDL
- SRAM
model
- Bus
model and arbitration
- memory
and bus in a microprocessor system
- Hardware
Testing
- testing
combinational logic
- testing
sequential logic
- scan
testing
- boundary
testing
- built-in
self test
- Design
Examples
- UART
design
- Microcontroller
CPU system