University of California, Davis
Department of Electrical and Computer Engineering

EEC 289Q - Reconfigurable Computing
Fall 2004
Lecture Notes and Slides

The slides used for lectures may have been borrowed from other researchers, who hold the copyright of their own piece of work. Besides citing and crediting their names in the lecture, clear notes have been put on the title page (and other slides) to acknowledge the source.

• Class 1 - 9/30
• Introduction to Topics
• Class 2 - 10/05
• Embedded Systems: Introduction and Design Automation
• Class 3 - 10/07
• Field Programmable Devices: Architecture
• Class 4 - 10/12
• High Level Synthesis: Scheduling and Integer Linear Programming (ILP)
• HW: Model Satisfiability problem (SAT) using ILP. SAT is the following problem: Given a (product of sums) Boolean expression determine if there is an assignment of 1’s and 0’s such that the expression evaluates to 1.
• Class 5 - 10/14
• Problem Complexity: A quick introduction to NP-Completeness
• HW: Prove that Dominating Set problem (are there B nodes in a graph that none of them are connected) is NP-complete. Hint: reduce Clique problem to dominating set.
• Class 6 - 10/19
• Some Required Algorithmic Techniques: Graph Coloring, Network Flows, Matching
• Class 7 - 10/21
• Power Driven Register Binding
• Class 8 - 10/26
• Logic Synthesis: Technology Mapping and Dynamic Programming
• Class 9 - 10/28
• Logic Synthesis: Technology Mapping for area and delay minimization
• Class 10 - 11/02
• Logic Synthesis: Technology Mapping for LUT-based FPGAs
• Class 11 - 11/04
• Placement
• Class 12 - 11/16
• Routing
• Class 13 – 11/18
• Class Presentations
• Class 14 - 11/23
• Dynamic Reconfiguration, Schedule Compression, Reconfiguration Delay Minimization