C.V. (Download PDF)

Jon J. Pimentel, Ph.D.


University of California, Davis

	Doctor of Philosophy, Electrical and Computer Engineering, August 2017
		Major: Digital Signals and Systems and Architectures
		Minor: Biomedical Imaging 
		GPA: 3.88/4.0
		Dissertation: "Methods for Reducing Floating-Point Computation Overhead."
		Advisor: Bevan M. Baas
	Master of Science, Electrical and Computer Engineering, December 2015
		GPA: 3.88/4.0
	Bachelor of Science, Electrical Engineering, June 2009
		GPA: 3.7/4.0

Research Experience

University of California, Davis

Graduate Student Researcher
September 2009 - 2016
  • Developing parallel synthetic aperture radar image processing application for 167 core chip
    • Creating image reconstruction algorithm to be mapped to many-core platform.
    • Wrote entire floating point software library for many-core platform.
    • Exploring tradeoffs in precision for area and power savings.
  • Designing and analyzing floating point software and hardware implementations
    • Developed many hybrid floating point units which to reduce area overhead while increasing throughput.
    • Creating non-conventional methods to perform floating point operations.
    • Synthesized designs in 65nm CMOS process.
  • Part of physical design team for next-generation many-core chip
    • Worked on physical design of my research group's many-core chip using Cadence Encounter.
    • Wrote scripts and performed logic-synthesis for meeting performance, power, and area targets.
    • Performed static timing analysis.
    • Setup standard cell library files and scripts.
  • Researched biomedical imaging modalities and signal processing algorithms
    • Explored mapping of magnetic resonance imaging application to 167-core many-core platform.
Undergraduate Researcher
January 2008 - September 2009
  • Responsible for setting up many-core processor test bench and characterizing variation
    • Implemented several kernels to run on 36 core AsAP 1 chip.
    • Wrote PERL test scripts for measuring various types of process variations.
    • Measured, simulated and analyzed multi-core processor hardware and applications.

Teaching Experience

Electrical & Computer Engineering Dept., University of California, Davis

Teaching Assistant
March 2016 - June 2016
  • EEC180B Digital Systems II
    • Grade Assignments
    • Course topics: Computer-aided design of digital systems with emphasis on hardware description languages, logic synthesis, and field-programmable gate arrays (FPGA). Advanced topics in digital system design such as static timing analysis, pipelining, memory system design, and testing digital circuits.
January 2015 - March 2015
  • EEC281: VLSI Digital Signal Processing
    • Grade Assignments
    • Course topics: Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
September 2012 - December 2012
  • EEC180A: Digital Systems I
    • Organizing and conducting weekly laboratory sessions for twenty undergraduate students.
    • Evaluating student lab reports and helping debug and design their circuits.
    • Holding weekly office hours and grading examinations.
    • Course topics: Combinational logic design, sequential circuits, computer arithmetic and digital system design; computer-aided design (CAD) methodologies and tools.

Industry Experience

Intel Corporation, Santa Clara, CA

Silicon Architecture Engineer
  • CPU microarchitect for power management
  • Defining architecture, RTL coding, and debugging logic issues
  • Delivering ROI, complexity, and schedule for next generation HPC project

Intel Corporation, Hillsboro, OR

Graduate Technical Intern
September 2013 - December 2013
  • Part of the MIC (many integrated core) design group working on next generation product.
  • Architecture definition, including mapping to micro-architecture implementation.

Technical Skills

  • CAD Tools: MATLAB and Simulink, Hspice; Cadence (NC Verilog, Simvision, Virtuoso); Synopsys (Design Compiler, PrimeTime); Altera and Xilinx FPGA tools.
  • Programming/RTL Languages: C, C++, LATEX, SystemVerilog/Verilog, Assembly, Python, UNIX Shell Script.


Publications in review are provided to sponsors but not yet listed here.

Professional Affiliations & Activities

  • Reviewer for IEEE Micro
  • Reviewer for IEEE Transactions on VLSI Systems (TVLSI)
  • Reviewer for IEEE Design and Test
  • Reviewer for Design Automation Conference (DAC)
  • Reviewer for IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
  • Reviewer for IEEE International Symposium on Circuits and Systems (ISCAS)
  • Member of Phi Kappa Phi Honor Society
  • Member of Tau Beta Pi Engineering Honor Society
  • Member of Golden Key International Honor Society
  • Member of Institute of Electrical & Electronics Engineers (IEEE)
  • Member of Portuguese American Post-Graduate Society


  • GAANN Fellowship (2009)
  • Graduate Research Mentorship Fellowship (2011)
  • UCD and Humanities Graduate Research Award (2012, 2014)
  • Frank and Carolan Walker Fellowship (2012, 2014, 2016)
  • George S. and Marjorie Butler Fellowship (2014)
  • ECE Graduate Program Fellowship (2014, 2015)
  • ECE TA Program Support Fellowship (2015)
  • Laura Perrot Mahan Fellowship (2016)
  • Herbert Tryon Fellowship (2015, 2016)
  • ECE Travel Grant Award (2016)
  • Dissertation Writing Fellowship (2016)
-Last updated: 08/09/2017