Solid-State Circuits Research Laboratory

Professor Stephen H. Lewis

Department of Electrical and Computer Engineering
University of California
Davis, California 95616
Phone: 530-752-0458
Fax: 530-752-8428
email: lewis at ece.ucdavis.edu

Courses Recently Taught:

ENG17, Circuits I, (syllabus)
ENG17H, Circuits I, (syllabus)
EEC110B, Electronic Circuits II, (syllabus)
EEC112, Communication Electronics, (syllabus)
EEC189S, MOS Analog Circuit Design, (syllabus)
EEC210, MOS Analog Circuit Design, (syllabus)
EEC213, Data Conversion Techniques and Circuits, (syllabus)

Research Area: Circuit Design for Signal Processing

Our group is working on circuit design for commercially significant signal-processing systems, including data conversion and communication. The key issues are to reduce the system cost and increase portability. This often requires both increased levels of integration and reduced power dissipations.

Journal Papers

T. A. Monk, P. J. Hurst, and S. H. Lewis, "Iterative Gain Enhancement in an Algorithmic ADC," IEEE Transactions on Circuits and Systems-I, Vol. 63, No. 4, pp. 459-469, Apr. 2016.

D. Wang, J. P. Keane, P. J. Hurst, and S. H. Lewis, "An Integrator-Based Pipelined ADC With Digital Calibration," IEEE Transactions on Circuits and Systems II, Vol. 62, No. 9, pp. 831-835, Sept. 2015.

N. C.-J. Chang,, P. J. Hurst, B. C. Levy, and S. H. Lewis, "Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors," IEEE Journal of Solid-State Circuits, Vol. 49, No. 6, pp. 1397-1407, Jun. 2014.

O. A. Hafiz, X. Wang, P. J. Hurst, and S. H. Lewis, "Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling," IEEE Journal of Solid-State Circuits, Vol. 48, No. 3, pp. 749-759, Mar. 2013.

S. Guhados, P. J. Hurst, and S. H. Lewis, "A Pipelined ADC With Metastability Error Rate < 10^-15 Errors/Sample," IEEE Journal of Solid-State Circuits, Vol. 47, No. 9, pp. 2119-2128, Sept. 2012.

K. A. O'Donoghue, P. J. Hurst, and S. H. Lewis, "A Digitally Corrected 5-mW 2-MS/s SC ΔΣ ADC in 0.25-μm CMOS With 94-dB SFDR," IEEE Journal of Solid-State Circuits, Vol. 46, No. 11, pp. 2673-2684, Nov. 2011.

K. Hosseini, M. P. Kennedy, S. H. Lewis, and B. C. Levy, "Prediction of the Spectrum of a Digital ΔΣ Modulator Followed by a Polynomial Nonlinearity," IEEE Transactions on Circuits and Systems I, pp. 1905-1913, Aug. 2010.

M. M. Zhang, P. J. Hurst, B. C. Levy, and S. H. Lewis, "Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver," IEEE Transactions on Circuits and Systems II, pp. 768-772, October 2009.

H. Wang, X. Wang, P. J. Hurst, and S. H. Lewis, "Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA," IEEE Journal of Solid-State Circuits, pp. 2780-2789, Oct. 2009,

T. Wang, D. Wang, P. J. Hurst, B. C. Levy, and S. H. Lewis, "A Level-Crossing Analog-to-Digital Converter With Triangular Dither," IEEE Transactions on Circuits and Systems I, pp. 2089-2099, Sept. 2009.

T.-H. Tsai, P. J. Hurst, and S. H. Lewis, "Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver," IEEE Transactions on Circuits and Systems I, pp. 307-319, Feb., 2009.

G. Xing, S. H. Lewis, and T. R. Viswanathan, "Self-Biased Unity-Gain Buffers with Low Gain Error," IEEE Transactions on Circuits and Systems II, pp. 36-40, Jan., 2009.

R. T. Perry, S. H. Lewis, A. Paul Brokaw, and T. R. Viswanathan. "A 1.4-V Supply CMOS Fractional Bandgap Reference," IEEE Journal of Solid-State Circuits, pp. 2180-2186, Oct., 2007.

N. J. Guilar, F. P.-K. Lau, P. J. Hurst, and S. H. Lewis, "A Passive Switched-Capacitor Finite-Impulse Response Equalizer," IEEE Journal of Solid-State Circuits, pp. 400-409, Feb., 2007.

T.-H. Tsai, P. J. Hurst, and S. H. Lewis, "Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters," IEEE Transactions on Circuits and Systems II, pp. 1133-1137, Oct., 2006.

J. P. Keane, P. J. Hurst, and S. H. Lewis, "Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters," IEEE Transactions on Circuits and Systems I, pp. 511-525, Mar., 2006.

C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MSample/s Pipelined ADC with Bootstrapped Background Calibration," IEEE Journal of Solid-State Circuits, pp. 1038-1046, May, 2005.

J. P. Keane, P. J. Hurst, and S. H. Lewis, "Background Interstage Gain Calibration Technique for Pipelined ADCs," IEEE Transactions on Circuits and Systems I, pp. 32-43, Jan., 2005.

X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit 20-MSample/s Pipelined Analog-to-Digital Converter with Nested Digital Background Calibration," IEEE Journal of Solid-State Circuits, pp. 1799-1808, Nov., 2004.

P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram, and K. C. Dyer, "Miller Compensation Using Current Buffers in Fully Differential CMOS Two-Stage Operational Amplifiers," IEEE Transactions on Circuits and Systems I, pp. 275-285, Feb., 2004.

S. M. Jamal, D. Fu, M. P. Singh, P. J. Hurst, and S. H. Lewis, "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter," IEEE Transactions on Circuits and Systems I, pp. 130-139, Jan., 2004.

E. B. Blecker, T. M. McDonald, O. E. Erdoğan, P. J. Hurst, and S. H. Lewis, "Digital Background Calibration of an Algorithmic Analog-to-Digital Converter Using a Simplified Queue," IEEE Journal of Solid-State Circuits, pp. 1059-1062, June, 2003.

S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, "A 10-b 120-MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration," IEEE Journal of Solid-State Circuits, pp. 1618-1627, Dec., 2002.

A. E. Buck, C. L. McDonald, S. H. Lewis, and T. R. Viswanathan, "A CMOS Bandgap Reference without Resistors," IEEE Journal of Solid-State Circuits, pp. 81-83, Jan., 2002.

J. Ming, and S. H. Lewis, "An 8-bit 80-MSample/s Pipelined ADC with Background Calibration," IEEE Journal of Solid-State Circuits, pp. 1489-1497, Oct., 2001.

O. Erdoğan, P. Hurst, and S. Lewis, "A 12-b Digital-Background-Calibrated Algorithmic ADC with -90dB THD," IEEE Journal of Solid-State Circuits, pp. 1812-1820, Dec., 1999.

J. Brown, P. Hurst, B. Rothenberg, and S. Lewis, "A CMOS Adaptive Continuous-Time Forward Equalizer, LPF, and RAM-DFE for Magnetic Recording," IEEE Journal of Solid-State Circuits, pp. 162-169, Feb., 1999.

D. Fu, K. Dyer, S. Lewis, and P. Hurst, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, pp. 1904-1911, Dec., 1998.

K. Dyer, D. Fu, S. Lewis, and P. Hurst, "An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, pp. 1912-1919, Dec., 1998.

C. K. Thanh, S. H. Lewis, and P. J. Hurst, "A Second-Order Double-Sampled Delta-Sigma Modulator using Individual-Level Averaging," IEEE J. of Solid-State Circuits, pp. 1269-1273, Aug., 1997.

B. C. Rothenberg, J. E. C. Brown, P. J. Hurst, and S. H. Lewis, "A Mixed-Signal RAM Decision-Feedback Equalizer for Disk Drives," IEEE J. of Solid-State Circuits, pp. 713-721, May, 1997.

K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW, 8-B, 52-Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers," IEEE Journal of Solid-State Circuits, pp. 312-320, Mar., 1997.

T. Shih, L. Der, S. H. Lewis, and P. J. Hurst, "A Fully Differential Comparator using a Switched-Capacitor Differencing Circuit with Common-Mode Rejection," IEEE J. of Solid-State Circuits, pp. 250-253, Feb., 1997.

T. V. Burmas, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Second-Order Double-Sampled Delta-Sigma Modulator Using Additive-Error Switching," IEEE J. of Solid-State Circuits, pp. 284-293, March, 1996.

B. C. Rothenberg, S. H. Lewis, P. J. Hurst, "A 20-MSample/s Switched-Capacitor Finite-Impulse-Response Filter using a Transposed Structure," IEEE J. of Solid-State Circuits, pp. 1350-1356, Dec., 1995.

J. F. Parker, K. W. Current, and S. H. Lewis, "A CMOS Continuous-Time NTSC to Color-Difference Decoder," IEEE J. of Solid-State Circuits, pp. 1524-1532, Dec., 1995.

P. J. Hurst and S. H. Lewis, "Determination of Stability Using Return Ratios in Balanced Fully Differential Feedback Circuits," IEEE Transactions on Circuits and Systems II, pp. 805-817, Dec., 1995.

K. Nagaraj, S. H. Lewis, R. W. Walden, G. E. Offord, R. S. Shariatdoust, J. A. Sabnis, R. O. Peruzzi, J. R. Barner, J. Plany, R. P. Mento, V. J. Rakshani, and R. W. Hull, "A Median Peak Detecting Analog Signal Processor for Hard Disk Drive Servo," IEEE Journal of Solid-State Circuits, pp. 461-470, Apr. 1995.

S. K. Berg, P. J. Hurst, and S. H. Lewis, "An 80-Msample/s Video Switched-Capacitor Filter using a Parallel Biquadratic Structure," IEEE Journal of Solid-State Circuits, pp. 898-905, Aug., 1995.

S. H. Lewis, R. Ramachandran, and W. M. Snelgrove, "Indirect Testing of Digital-Correction Circuits in Analog-to-Digital Converters with Redundancy," IEEE Transactions on Circuits and Systems II, pp. 437-445, Jul., 1995.

S. H. Lewis, "Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications," IEEE Transactions on Circuits and Systems II, pp. 516-523, Aug., 1992.

S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-B 20-Msample/s Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, pp. 351-358, Mar., 1992.

S. H. Lewis and P. R. Gray, "A Pipelined 5 MS/s 9-bit Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, pp. 954-961, Dec. 1987.

Conference Papers

M. M. Zhang, P. J. Hurst, and S. H. Lewis, "An Algorithmic ADC with Greater Than Rail-to-Rail Input Range and Near-Vt Supply," Proceedings of the ISCAS, Montreal Canada, pp. 81-84, Jun. 2016.

N. C.-J. Chang, P. J. Hurst, B. C. Levy, and S. H. Lewis, "Background Adaptive Cancellation of Digital Switching Noise in Pipelined ADCs," IEEE Custom Integrated Circuits Conference, October, 2012.

K. A. O'Donoghue, P. J. Hurst, and S. H. Lewis, "A Digitally Calibrated 5-mW 2-MS/s 4th-Order ΣΔ ADC in 0.25-μm CMOS with 94 dB SFDR," European Solid-State Circuits Conference, pp. 422-425, Sept. 2010.

O. E. Gysel, P. J. Hurst, and S. H. Lewis, "Highly Programmable Switched-Capacitor Filters Using Biquads with Nonuniform Internal Clocks," Systems on a Chip Conference, pp. 33-38, Sept., 2010.

M. M. Zhang, P. J. Hurst, B. C. Levy, and S. H. Lewis, "Calibration of Pipelined ADC Gain and Memory Errors in an Adaptively Equalized Receiver," IEEE International Symposium on Circuits and Systems, pp. 4049-4052, May, 2010.

N. Guilar, R. Amirtharajah, P. Hurst and S. Lewis, "An Energy-Aware Multiple-Input Power Supply with Charge Recovery for Energy Harvesting Applications", IEEE Int'l Solid-State Circuits Conf., pp. 298-299, Feb. 2009.

G. Xing, S. H. Lewis, and T. R. Viswanathan, "A Unity-Gain Buffer with Reduced Offset and Gain Error," IEEE Custom Integrated Circuits Conference, pp. 825-828, Sept., 2006.

R. T. Perry, S. H. Lewis, A. P. Brokaw, and T. R. Viswanathan, "A 1.4-V Supply CMOS Fractional Bandgap Reference," IEEE VLSI Symposium, pp. 102-103, June, 2006.

N. J. Guilar, P.-K. Lau, P. J. Hurst, and S. H. Lewis, "A 200 MS/s Passive Switched-Capacitor FIR Equalizer using a Time-Interleaved Topology," IEEE Custom Integrated Circuits Conference, pp. 633-636, Sept., 2005.

D. Wang, J. P. Keane, P. J. Hurst, B. C. Levy, and S. H. Lewis, "Convergence Analysis of a Background Interstage Gain Calibration Technique for Pipelined ADCs," IEEE International Symposium on Circuits and Systems, pp. 4058-4061, May, 2005.

C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MS/s Pipelined ADC with Bootstrapped Digital Calibration," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 460-461, Feb. 2004. (Beatrice Winner Award for Editorial Excellence)

T.-H. Tsai, P. J. Hurst, and S. H. Lewis, "Time Interleaved Analog-to-Digital Converters for Digital Communications," IASTED International Conference on Circuits, Signals, and Systems, pp. 193-198, Nov., 2004.

J. P. Keane, P. J. Hurst, and S. H. Lewis, "Modeling Memory Errors in Pipelined Analog-to-Digital Converters," IASTED International Conference on Circuits, Signals, and Systems, pp. 136-141, Nov., 2004.

X. Wang, P. J. Hurst, S. H. Lewis, "A 12-bit 20-MS/s Pipelined ADC with Nested Digital Background Calibration," Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, pp. 409-412, Sep., 2003.

A. Acharya, P. J. Hurst, and S. H. Lewis, "Thermal Noise From Switches in a Switched-Capacitor Gain Stage," Southwest Symposium on Mixed-Signal Design, pp. 121-126, Feb., 2003.

S. M. Jamal, D. Fu, P. J. Hurst, and S. H. Lewis, "A 10b 120Msample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 172-173, Feb., 2002.

E. B. Blecker, O. E. Erdoğan, P. J. Hurst, and S. H. Lewis, "An 8-bit 13-Msamples/s Digital-Background-Calibrated Algorithmic ADC," Proceedings of the 26th European Solid-State Circuit Conference, pp. 372-375, Sep., 2000.

A. Buck, C. McDonald, S. Lewis, and T. R. Viswanathan, "A CMOS Bandgap Reference without Resistors," International Solid-State Circuits Conference, pp. 442-443, Feb., 2000. (Jack Kilby Award for Outstanding Student Paper)

J. Ming and S. Lewis, "An 8b 80Msample/s Pipelined ADC with Background Calibration," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 42-43, Feb., 2000.

O. Erdoğan, P. Hurst, and S. Lewis, "A 12-b Digital-Background-Calibrated Algorithmic ADC with -90dB THD," International Solid-State Circuits Conference, pp. 316-317, Feb., 1999. (Beatrice Winner Award for Editorial Excellence, Honorable Mention)

K. Dyer, D. Fu, P. Hurst, and S. Lewis, "A Comparison of Monolithic Background Calibration in Two Time-Interleaved Analog-to-Digital Converters," IEEE International Symposium on Circuits and Systems, pp. I-13 - I-16, May, 1998.

D. Fu, K. Dyer, S. Lewis, and P. Hurst, "Digital Background Calibration of a 10b 40MSample/s Parallel Pipelined ADC," International Solid-State Circuits Conference, pp. 140-141, Feb., 1998.

K. Dyer, D. Fu, S. Lewis, and P. Hurst, "Analog Background Calibration of a 10b 40MSample/s Parallel Pipelined ADC," International Solid-State Circuits Conference, pp. 142-143, Feb., 1998.

J. Brown, P. Hurst, B. Rothenberg, and S. Lewis, "An 80 Mb/s Adaptive DFE Detector in 1 μm CMOS," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 324-325, Feb., 1997.

B. C. Rothenberg, J. E. C. Brown, P. J. Hurst, and S. H. Lewis, "A Mixed-Signal RAM Decision-Feedback Equalizer for Disk Drives," Digest of Technical Papers, IEEE 1996 Symposium on VLSI Circuits, pp. 180-181, Jun. 1996.

C. Thanh, S. H. Lewis, P. J. Hurst, "A 2nd-Order Double-Sampled Delta Sigma Modulator with Individual-Level Averaging," Digest of Technical Papers, IEEE 1996 Symposium on VLSI Circuits, pp. 100-101, Jun. 1996.

K. Nagaraj, H. S. Fetterman, R. S. Shariatdoust, J. Anidjar, S. H. Lewis, J. Alsayegh, and R. G. Renninger, "An 8-bit 50+ Msamples/s Pipelined A/D Converter with an Area and Power Efficient Architecture," Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, pp. 423-426, May 1996.

T. V. Burmas, S. H. Lewis, P. J. Hurst, and K. C. Dyer, "A Second-Order Double-Sampled Delta-Sigma Modulator," Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 195-198, May 1995.

B. C. Rothenberg, S. H. Lewis, P. J. Hurst, "A 20 Msample/s Switched-Capacitor Finite Impulse Response Filter in 2-micron CMOS," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 210-211, Feb., 1995.

J. F. Parker, K. W. Current, and S. H. Lewis, "A CMOS Continuous-Time NTSC To Color-Difference Decoder," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 294-295, Feb., 1995.

K. Nagaraj, R. W. Walden, G. E. Offord, S. H. Lewis, J. A. Sabnis, R. O. Peruzzi, J. R. Barner, J. Plany, R. P. Mento, V. J. Rakshani, and R. W. Hull, "A Median Peak Detecting Servo Analog Processor for Hard Disk Drives," Digest of Technical Papers, IEEE 1994 Symposium on VLSI Circuits, pp. 91-92, Jun. 1994.

P. J. Hurst and S. H. Lewis, "Simulation of Return Ratio in Fully Differential Feedback Circuits," Proceedings of the IEEE 1994 Custom Integrated Circuits Conference, pp. 29-32, May, 1994.

S. K. Berg, P. J. Hurst, S. H. Lewis, and P. T. Wong, "A Switched-Capacitor Filter in 2-micron CMOS using Parallelism to Sample at 80 MHz," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 62-63, Feb., 1994.

L. Der, S. H. Lewis, and P. J. Hurst, "A Switched-Capacitor Differencing Circuit with Common-Mode Rejection for Fully Differential Comparators," Proceedings of the 36th Midwest Symposium on Circuits and Systems, pp. 911-914, Aug., 1993.

S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, "A Pipelined 9-Stage Video-Rate Analog-to-Digital Converter," Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, pp. 26.4.1-26.4.4, May, 1991.

S. H. Lewis and P. R. Gray, "Circuit Techniques for Monolithic CMOS Video Analog-to-Digital Conversion," Digest of Technical Papers, IEEE International Symposium on Circuits and Systems, pp. 1092-1095, May, 1987.

S. H. Lewis and P. R. Gray, "A Pipelined 5MHz 9b ADC," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 210-211, Feb., 1987. (Beatrice Winner Award for Editorial Excellence) (ISSCC 50th Anniversary Museum Paper)

Books

P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, "Analysis and Design of Analog Integrated Circuits," 5th Edition, Wiley, New York, 2009

P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, "Analysis and Design of Analog Integrated Circuits," 4th Edition, Wiley, New York, 2001

Professional Activities

President, IEEE Solid-State Circuits Society, January 2004 - December 2005.

Editor in Chief, IEEE Journal of Solid-State Circuits, July 1998 - July 2001.

Associate Editor, IEEE Journal of Solid-State Circuits, January 1994 - December 1997.

Program Committee Member, International Solid-State Circuits Conf., June 1993 - Feb. 1998.

Awards

IEEE Professor of the Year, UC Davis, 2016

College of Engineering Outstanding Faculty Teaching Award, UC Davis, 2013

IEEE Professor of the Year, UC Davis, 2010

ASUCD Excellence in Education Award for the College of Engineering for 2009

Lockheed Martin Teaching Excellence Award for an Associate or Full Professor, 2008

Editorial Excellence with Dr. C. R. Grace and Prof. P. J. Hurst 2004 IEEE International Solid-State Circuits Conference (ISSCC)

ISSCC 50-Year Anniversary Author Honor Roll

ISSCC 50-Year Anniversary Museum Paper

IEEE Fellow, 2001

Outstanding Student Paper with Mr. A. E. Buck, Mr. C. L. McDonald, and Dr. T.R. Viswanathan, 2000 ISSCC

IEEE Third Millennium Medal recipient, 2000

Editorial Excellence (Honorable Mention) with Dr. O. E. Erdoğan and Prof. P.J. Hurst, 1999 ISSCC

Evening Session Award (for leadership in organizing the best panel discussion), 1994 ISSCC

Research Initiation Award, 1992 National Science Foundation

Sakrison Memorial Prize (best Ph.D. thesis in EECS), 1988 University of California

Editorial Excellence with Prof. Paul R. Gray, 1987 ISSCC

Outstanding Engineering Scholar, 1979 Rutgers University

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