# Professor Paul J. Hurst

## Publications

M.M. Zhang, P.J. Hurst, and S.H. Lewis,
"An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply",
IEEE International Symposium on Circuits and
Systems, pp. 81-84, Montreal, May, 2016.

T.A. Monk, P.J. Hurst, and S.H. Lewis,
"Iterative Gain Enhancement in an Algorithmic ADC",
IEEE Transactions on Circuits and Systems I: Regular Papers,
pp 459 - 469, April 2016.

Ofer Rozen, Scott T. Block, Xuan Mo, Westley Bland, Paul Hurst, Julius. M. Tsai, Mike Daneman, Rajeevan Amirtharajah and David A. Horsley
"Monolithic MEMS-CMOS ultrasonic rangefinder based on dual-electrode PMUTs",
IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS),
pp. 115 - 118,
Shanghai, Jan. 2016.

D. Wong, J. Keane, P. Hurst and S. Lewis,
"An Integrator-Based Pipelined ADC With Digital Calibration",
IEEE Trans. on Circuits and Systems II, pp. 831-835, Sept. 2015.

N.C.-J Chang, P.J. Hurst, B.C. Levy and S.H. Lewis, "Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digtal
Converter without Noise Sensors",
IEEE Journal of Solid-State Circuits, pp. 1397-1407, June 2014.

O.A. Hafiz, X. Wang, P.J. Hurst, and S.H. Lewis, "Immediate Calibration of Operational
Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling",
IEEE Journal of Solid-State Circuits, pp. 749-759, March 2013.

L.P. Rao, N. Sitthimahachaikul and P.J. Hurst,
"Correcting the Effects of Mismatch in Time-Interleaved Analog Adaptive FIR
Equalizers",
IEEE Trans. on Circuits and Systems I, pp. 2529-2542, Nov. 2012.

S. Guhados, P.J. Hurst and S.H. Lewis,
"A Pipelined ADC with Metastability Error Rate <10^-15 Errors/Sample",
IEEE Journal of Solid-State Circuits, pp. 2119-2128, Sep. 2012.

N. C.-J. Chang, P.J. Hurst, B.C. Levy and S.H. Lewis,
"Background Adaptive Cancellation of Digital Switching Noise in
Pipelined ADCs without Noise Sensors",
IEEE Custom Integrated Circuits Conf., 4 pages, paper T-1, San Jose, Sept. 2012.

N. Sitthimahachaikul, L.P. Rao and P.J. Hurst,
"Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer
Forward Equalizer",
IEEE Trans. on Circuits and Systems II, pp. 188-192, Mar. 2012.

N. Sitthimahachaikul, L.P. Rao and P.J. Hurst,
"Overcoming the Effect of the Summation-Node Parasitic Pole
in an Analog Equalizer",
IEEE Trans. on Circuits and Systems I, pp. 652-663, Mar. 2012.

K.A. O'Donoghue, P.J. Hurst and S.H. Lewis,
"A Digitally Corrected 5-mW 2-MS/s SC Delta-Sigma ADC in 0.25um CMOS
with 94-dB SFDR",
IEEE Journal of Solid-State Circuits, pp. 2673-2684, Nov. 2011.

C.-H. Law, P.J. Hurst and S.H. Lewis,
"A 4-Channel Time-Interleaved ADC with Digital Calibration
of Interchannel Timing and Memory Errors",
IEEE Journal of Solid-State Circuits, pp. 2091-2103, Oct. 2010.

O.E. Gysel, P.J. Hurst and S.H. Lewis,
"Highly Programmable Switched-Capacitor Filters Using Biquads
with Nonuniform Internal Clocks",
IEEE System on Chip Conf., Las Vegas, pp. 33-38, Sept. 2010.

K.A. O'Donoghue, P.J. Hurst, and S.H. Lewis,
"A Digitally Calibrated 5-mW 2-MS/s 4th-Order
Delta-Sigma ADC in 0.25-um CMOS with 94dB SFDR,"
Proc. of the European Solid-State Circuits Conf., Seville,
pp. 422-425, Sept. 2010.

M.M. Zhang, P.J. Hurst, B.C. Levy, and S.H. Lewis,
"Calibration of Pipelined ADC Gain and
Memory Errors in an Adaptively Equalized Receiver",
IEEE International Symposium on Circuits and
Systems, pp. 4049-4052, Paris, 30 May - 2 June, 2010.

P. Satarzadeh, B.C. Levy and P.J. Hurst,
"A Parametric Polyphase Domain Approach
to Blind Calibration of Timing Mismatches for M-Channel Time-Interleaved
ADCs",
IEEE International Symposium on Circuits and
Systems, pp. 4053-4056, Paris, 30 May - 2 June, 2010.

H. Wang, X. Wang, P. Hurst and S. Lewis,
"Nested Digital Background Calibration of a 12-bit Pipelined
ADC without an Input SHA",
IEEE Journal of Solid-State Circuits, pp. 2780-2789, Oct. 2009.

M.M. Zhang, P.J. Hurst, B.C. Levy and S.H. Lewis,
"Gain-Error Calibration of a Pipelined ADC in an
Adaptively Equalized Baseband Receiver,"
IEEE Trans. on Circuits and Systems II, pp. 768-772, Oct. 2009.

P. Satarzadeh, B.C. Levy, and P.J. Hurst,
"Adaptive Semiblind Calibration of Bandwidth Mismatch for
Two-Channel Time-Interleaved ADCs,"
IEEE Trans. on Circuits and Systems I, pp. 2075-2088, Sept. 2009.

T. Wang, D. Wang, P.J. Hurst, B.C. Levy, and S.H. Lewis,
"A Level-Crossing Analog-to-Digital Converter With Triangular Dither,"
IEEE Trans. on Circuits and Systems I, pp. 2089-2099, Sept. 2009.

P. Satarzadeh, B.C. Levy, and P.J. Hurst,
"Digital calibration of a Nonlinear
S/H,"
IEEE Journal of Selected Topics in Signal Processing, pp. 454-471, June 2009.

T.-H. Tsai, P. Hurst and S. Lewis,
"Correction of Mismatches in a Time-Interleaved
Analog-to-Digital Converter in an Adaptively Equalized
Digital Communication Receiver,"
IEEE Trans. on Circuits and Systems I, pp. 307-319, Feb. 2009.

N. Guilar, R. Amirtharajah, P. Hurst and S. Lewis,
"An Energy-Aware Multiple-Input Power Supply with Charge Recovery
for Energy Harvesting Applications",
IEEE Int'l Solid-State Circuits Conf., pp. 298-299,
Feb. 2009.

N. Guilar, R Amirtharajah, and P. Hurst,
"A Full-Wave Rectifier for Interfacing with Multi-Phase
Piezoelectric Energy Harvesters",
IEEE Journal of Solid-State Circuits, pp. 240-246, Jan. 2009.

P. Hurst and A. Norrell HERE,
"DAC Quantization-Noise Cancellation in an
Echo-Cancelling Transceiver,"
IEEE Trans. on Circuits and Systems II, pp. 111-115,
P. Hurst and A. Norrell,
"DAC Quantization-Noise Cancellation in an
Echo-Cancelling Transceiver,"
IEEE Trans. on Circuits and Systems II, pp. 111-115,
Feb. 2008.

N. Guilar, R. Amirtharajah, P. Hurst, D. Margolis, and D. Horsley,
"Interface Circuits for
Multiphase Piezoelectric Energy Harvesters,"
IEEE Applied Power
Electronics Conference, Austin, pp. 639-644, Feb. 2008.

R.A. Hershbarger, W. Jia, K.M. Tiam, K. Fukahori, P. Hurst, and M. Kapoor,
"A Programmable Impedance Matching Circuit for
Voiceband Modems,"
IEEE Journal of Solid-State Circuits, pp. 468-476,
Feb. 2008.

N. Guilar, R. Amirtharajah and P. Hurst,
"A Full-Wave Rectifier for Interfacing with Multi-Phase
Piezoelectric Energy Harvesters",
IEEE Int'l Solid-State Circuits Conf., pp. 302-303 and p. 615,
Feb. 2008.

N. Guilar, R. Amirtharajah and P. Hurst,
"Analysis of DC-DC Conversion for Energy Harvesting Systems
Using a Mixed-Signal Sliding-Mode Controller",
IEEE Power Electronics
Specialist Conference, Orlando, June 2007.

P. Satarzadeh, B.C. Levy and P.J. Hurst,
"Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved
A/D Converter,"
IEEE Int'l Symposium on Circuits and Systems, 4 pages, New Orleans, May 2007.

N. Guilar, P. Hurst, and S. Lewis,
"A Passive Switched-Capacitor Finite-Impulse-Response Equalizer",
IEEE Journal of Solid-State Circuits, pp. 400-409, Feb. 2007.

T.-H. Tsai, P. Hurst and S. Lewis,
"Bandwidth Mismatch Correction in Time-Interleaved
Analog-to-Digital Converters,"
IEEE Trans. on Circuits and Systems II, pp. 1133-1137, Oct. 2006.

M.M. Zhang and P.J. Hurst,
"Effect of Nonlinearity in the CMFB Circuit that Uses
the Differential-Difference Amplifier,"
IEEE Int'l Symposium on Circuits and Systems, pp. 1390-1393, Kos Island, Greece, May 2006.

J. Keane, P. Hurst and S. Lewis,
"Digital Background Calibration for Memory Effects in
Pipelined Analog-to-Digital Converters,"
IEEE Trans. on Circuits and Systems I, pp. 511-525, Mar. 2006.

N. Guilar, P. Hurst, and S. Lewis,
"A 200MS/s Passive Switched-Capacitor FIR Equalizer using a
Time-Interleaved Topology",
IEEE Custom Integrated Circuits Conf., pp. 633-636, San Jose, Sept. 2005.

C. Grace, P. Hurst, and S. Lewis,
"A 12-bit 80-Msample/s Pipelined ADC
with Bootstrapped Digital Calibration,"
IEEE Journal of Solid-State Circuits, pp. 1038-1046,
May 2005.

D. Wang, J. Keane, B. Levy, P. Hurst, and S. Lewis,
"Convergence Analysis of a Background Interstage Gain
Calibration Technique for Pipelined ADCs,"
IEEE Int'l Symposium on Circuits and Systems, pp. 4058-4061, Kobe, Japan, May 2005.

J. Keane, P. Hurst and S. Lewis,
"Background Interstage Gain Calibration
Technique for Pipelined ADCs,"
IEEE Trans. on Circuits and Systems I, pp. 32-43, Jan. 2005.

X. Wang, P. Hurst, and S. Lewis,
"A 12-bit 20-Msample/s Pipelined Analog-to-Digital Converter
with Nested Digital Background Calibration,"
IEEE Journal of Solid-State Circuits, pp. 1799-1808,
Nov. 2004.

T.-H. Tsai, P.J. Hurst and S.H. Lewis,
"Time-Interleaved Analog-to-Digital Converters
for Digital Communications,"
Conf. on Circuits, Signals and Systems, pp. 193-198,
Nov. 2004.

J.P. Keane, P.J. Hurst and S.H. Lewis,
"Modeling Memory Errors in Pipelined Analog-to-Digital
Converters,"
Conf. on Circuits, Signals and Systems, pp. 136-141,
Nov. 2004.

R. Prendergast, B. Levy, and P. Hurst,
"Reconstruction of Bandlimited Periodic Nonuniformly
Sampled Signals through Multirate Filter Banks,"
IEEE Trans. on Circuits and Systems I, pp. 1612-1622, August 2004.

J. Keane and P. Hurst,
"Timing Recovery for the Magnetic Recording Channel
using the Wave Difference Method,"
IEEE Trans. on Magnetics, pp. 3102-3104, July 2004.

A. Tong and P. Hurst,
"A Mixed-Signal Approach for Tuning
Continuous-Time Low-Pass Filters,"
IEEE Trans. on Circuits and Systems II, pp. 307-314, June 2004.

N. Sittimahachaikul, J. Keane and P. Hurst,
"An Adaptive DFE using an IIR Feedback Equalizer
for 100Base-Tx Ethernet,"
IEEE Northeast Workshop on Circuits and Systems, pp. 173-176, Montreal, June 2004.

P. Hurst, S. Lewis, J. Keane, F. Aram, and K. Dyer,
"Miller Compensation
Using Current Buffers in Fully Differential CMOS Two-Stage Operational
Amplifiers,"
IEEE Trans. on Circuits and Systems I, pp. 275-285, Feb. 2004.

C. Grace, P. Hurst, and S. Lewis,
"A 12b 80MS/s Pipelined ADC with Boostrapped Digital
Calibration,"
IEEE Int'l Solid-State Circuits Conf., pp. 460-461 and p. 539,
Feb. 2004.

S. Jamal, D. Fu, M. Singh, P. Hurst, and S. Lewis,
"Calibration of Sample-Time
Error in a Two-Channel Time-Interleaved
Analog-to-Digital Converter,"
IEEE Trans. on Circuits and Systems I, pp. 130-139, Jan. 2004.

J.P. Keane and P.J. Hurst,
"Timing Recovery for the Magnetic Recording Channel
Using the Wave Difference Method,"
MMM/Intermag Conf., Anaheim, Jan. 2004.

L.P. Rao, M.Q. Le, J.P. Keane, and P.J. Hurst,
"Performance Comparison of Noise-Predictive DFE and PRML Detectors,"
MMM/Intermag Conf., Anaheim, Jan. 2004.

X.Y. Wang, P.J. Hurst, and S.H. Lewis,
"A 12-bit 20-MS/s Pipelined ADC with Nested Digital Background
Calibration,"
IEEE Custom IC Conf., San Jose, pp. 409-412, Sept. 2003.

E.B. Blecker, T.M. McDonald, O.E. Erdogan, P.J. Hurst, and S.H. Lewis,
"Digital-Background Calibration of an Algorithmic ADC Using a Simplified Queue,"
IEEE Journal of Solid-State Circuits, pp. 1059-1062,
June 2003.

J.P. Keane, M.Q. Le and P.J. Hurst,
"Analog Timing Recovery for a Noise-Predictive DFE,"
IEEE Journal of Solid-State Circuits, pp. 338-342,
Feb. 2003.

A. Acharya, P.J. Hurst, and S.H. Lewis,
"Thermal Noise from Switches in a Switched-Capacitor Gain Stage,"
Proc. of the Southwest Symp. on Mixed-Signal Design, pp. 121-126, Las Vegas,
Feb. 2003.

S.M. Jamal, D. Fu, N. C.-J. Chang, P.J. Hurst, and S.H. Lewis,
"A 10-bit 120MS/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration,"
IEEE Journal of Solid-State Circuits, pp. 1618-1627,
Dec. 2002.

R.S. Prendergast, B.C. Levy and P.J. Hurst,
"Multirate Filter Bank Reconstruction of Bandlimited Signals from Bunched Samples,"
Asilomar Conference on Signals, Systems, and Computers,
Pacific Grove/Monterey, pp. 781-785, Nov. 2002.

J.P. Keane, M.Q. Le and P.J. Hurst,
"Analog Timing Recovery for a Noise-Predictive DFE,"
Proc. of the European Solid-State Circuits Conf., Florence, pp. 243-246,
September 2002.

A. Lee, P. Hurst and K. Fukahori,
"CMOS Circuits for Thermal Asperity Detection and Recovery
in Disk-Drive Read Channels,"
Midwest Symp. on Circuits and Systems, Tulsa, pp. III-364 to III-367, August 2002.

S.M. Jamal, D. Fu, P.J. Hurst, and S.H. Lewis,
"A 10-bit 120MS/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration,"
IEEE Int'l Solid-State Circuits Conf., pp. 172-173 and 457, S.F.,
Feb. 2002.

M.Q. Le, P.J. Hurst and J.P. Keane,
"An Adaptive Analog Noise-Predictive Decision-Feedback Equalizer,"
IEEE J. of Solid-State Circuits, pp. 105-113, Feb. 2002.

A. Tong and P. Hurst,
"A Mixed-Signal Tuning Approach for Continous-Time LPFs,"
IEEE Int'l Symposium on Circuits and Systems, pp. I-192-I-195, Sydney, May 2001.

P. Gray, P. Hurst, S. Lewis and R. Meyer,
"Analysis and Design of Analog Integrated Circuits,"
4th edition, Wiley, March 2001.

A. Gattani, D.W. Cline, P.J. Hurst and P.M. Mosinskis,
"A CMOS HDSL2 Analog Front-End,"
IEEE Journal of Solid-State Circuits,
pp. 1964-1975, Dec. 2000.

E.B. Blecker, O.E. Erdogan, P.J. Hurst, and S.H. Lewis,
"An 8-Bit 13-MSamples/s Digital-Background-Calibrated Algorithmic ADC,"
Proc. of the European Solid-State Circuits Conf., Stockholm, pp. 372-375,
September 2000.

R.W. Zeng and P.J. Hurst,
"A Comparison of Noise-Shaping Clock Generators for Switched-Capacitor Filters,"
IEEE Trans. on Circuits and Systems-II, pp. 544-547, June 2000.

M.Q. Le, P.J. Hurst and J.P. Keane,
"An Adaptive Analog Noise-Predictive Decision-Feedback Equalizer,"
IEEE & JSAP Symposium on VLSI Circuits, Honolulu, pp. 216-217,
June 2000.

A. Gattani, D.W. Cline, P.J. Hurst and P.M. Mosinskis,
"A CMOS HDSL2 Analog Front-End,"
IEEE Int'l Solid-State Circuits Conf., S.F.,
pp. 302-303, Feb. 2000.

P. Roo, R. Spencer and P. Hurst,
"A CMOS Analog Timing Recovery Circuit for
PRML Detectors,"
IEEE J. of Solid-State Circuits, pp. 56-65, Jan. 2000.

O.E. Erdogan, P.J. Hurst and S.H. Lewis,
"A 12-b Digital-Background-Calibrated Algorithmic ADC with -90dB THD,"
IEEE J. of Solid-State Circuits, pp. 1812-1820, Dec. 1999.

M. Le, P.J. Hurst and X. Wang,
"An Adaptive Noise-Predictive Decision-Feedback Equalizer for the
Magnetic Recording Channel," IEEE Pacific
Rim Conference on Communications, Victoria, B.C., pp. 560-563, August 1999.

M.Q. Le, P.J. Hurst and K.C. Dyer,
"An Analog DFE for Disk Drives Using a Mixed-Signal Integrator,"
IEEE J. of Solid-State Circuits, pp. 592-598, May 1999.

O.E. Erdogan, P.J. Hurst and S.H. Lewis,
"A 12-b Digital-Background-Calibrated Algorithmic ADC with -90dB THD,"
IEEE Int'l Solid-State Circuits Conf., S.F.,
pp. 316-317 & 473 Feb. 1999.

J.E.C. Brown, P.J. Hurst, B.C. Rothenberg and S.H. Lewis,
"A CMOS Adaptive Continuous-Time Forward Equalizer, LPF and RAM-DFE for Magnetic Recording,"
IEEE J. of Solid-State Circuits, pp. 162-169, Feb. 1999.
*(figures)*

J. Everitt, J. Parker, P. Hurst, D. Nack and K. Konda, "A 100Mb/s CMOS
Ethernet Transceiver," IEEE J. of Solid-State Circuits, pp. 2169-2177, Dec. 1998.

D. Fu, K. Dyer, S. Lewis and P. Hurst,
"A Digital Background Calibration Technique for Time-Interleaved ADCs,"
IEEE J. of Solid-State Circuits, pp. 1904-1911, Dec. 1998.
*(figures)*

K. Dyer, D. Fu, S. Lewis and P. Hurst,
"An Analog Background Calibration Technique for Time-Interleaved ADCs,"
IEEE J. of Solid-State Circuits, pp. 1912-1919, Dec. 1998.
*(figures)*

J. Brown and P. Hurst,
"Continuous-Time Forward Equalization for the DFE-based Read Channel",
IEEE Trans. on Magnetics, pp. 2372-2381,
July 1998.

M. Le, P.J. Hurst and K. C. Dyer,
"An Analog Decision-Feedback Equalizer That Uses a Mixed-Signal Integrator," IEEE & JSAP Symposium on VLSI Circuits, Honolulu, pp.
180-181, June 1998.

K. Dyer, D. Fu, P. Hurst and S. Lewis,
"A Comparison of Monolithic Background Calibration in Two Time-Interleaved Analog-to-Digital Converters,"
IEEE Int'l Symposium on Circuits and Systems, 4 pages, Monterey, May 1998.

J. Everitt, J. Parker, P. Hurst, D. Nack, K. Konda and C. Raad, "A 10/100Mb/s CMOS
Ethernet Transceiver for 10BaseT, 100BaseT, and 100BaseFX," IEEE Int'l Solid-State
Circuits Conf., S.F., pp. 210-211, Feb. 1998.

D. Fu, K. Dyer, S. Lewis and P. Hurst, "Digital Background Calibration of a 10b
40MSample/s Parallel Pipelined ADC," IEEE Int'l Solid-State Circuits Conf., S.F., pp.
140-141 & 426, Feb. 1998.

K. Dyer, D. Fu, S. Lewis and P. Hurst, "Analog Background Calibration of a 10b
40MSample/s Parallel Pipelined ADC," IEEE Int'l Solid-State Circuits Conf., S.F., pp.
142-143 & 427, Feb. 1998.

P. Roo, R. Spencer and P. Hurst, "A CMOS Analog Timing Recovery Circuit for
180Mb/s PRML Detectors," IEEE Int'l Solid-State Circuits Conf., S.F., pp. 392-393 &
471, Feb. 1998.

C.K. Thanh, S.H. Lewis and P.J. Hurst,
"A Second-Order Double-Sampled Delta-Sigma Modulator with Individual-Level Averaging,"
IEEE J. of Solid-State Circuits, pp. 1269-1273, August 1997.

B.C. Rothenberg, J.E.C. Brown, P.J. Hurst and S.H. Lewis, "A Mixed-Signal RAM
Decision-Feedback Equalizer for Disk Drives," IEEE J. of Solid-State Circuits, pp. 713-
721, May 1997.

R.S. Kajley, P.J. Hurst and J.E.C. Brown, "A Mixed-Signal Decision-Feedback Equalizer
That Uses a Look-Ahead Architecture," IEEE J. of Solid-State Circuits, pp. 450-459,
March 1997.

T. Shih, L. Der, S.H. Lewis and P.J. Hurst,
"A Fully Differential Comparator Using a Switched-Capacitor Differencing Circuit with Common-Mode Rejection",
IEEE J. of Solid-State Circuits, pp. 250-253, February 1997.

J.E.C. Brown, P.J. Hurst, B. Rothenberg and S. Lewis,
"An 80 Mb/s Adaptive DFE Detector in 1um CMOS,"
IEEE Int'l Solid-State Circuits Conf., S.F., pp. 324-325 & 480, Feb. 1997.

J.E.C. Brown, P.J. Hurst and L. Der,
"A 35 Mb/s Mixed-Signal Decision-Feedback Equalizer for Disk-Drives in 2um CMOS,"
IEEE J. of Solid-State Circuits, pp. 1258-1266, Sept. 1996.
*(figures)*

C. Thanh, S.H. Lewis and P.J. Hurst, "A Second-Order Double-Sampled DSM with
Individual-Level Averaging," IEEE & JSAP Symposium on VLSI Circuits, Honolulu, pp.
100-101, June 1996.

B.C. Rothenberg, J.E. Brown, P.J. Hurst and S.H. Lewis,
"A Mixed-Signal RAM Decision-Feedback Equalizer for Disk Drives,"
IEEE & JSAP Symposium on VLSI Circuits, Honolulu,
pp. 180-181, June 1996.

R.W. Zeng and P.J. Hurst,
"A comparison of noise-shaping clock generators for switched-capacitor filters,"
IEEE Int'l Symposium on Circuits and Systems, Atlanta, vol. 1, pp. 77-80, May 1996.

R.S. Kajley, J.E. Brown and P.J. Hurst,
"A mixed-signal DFE that uses parallelism,"
IEEE Custom IC Conf., San Diego, pp. 17-20, May 1996.

T.V. Burmas, K.C. Dyer, P.J. Hurst and S.H. Lewis,
"A Second-Order Double-Sampled Delta-Sigma Modulator Using Additive-Error Switching,"
IEEE J. of Solid-State Circuits, pp. 284-293, March 1996.

P.J. Hurst, "Operational Amplifiers," in The Engineering Handbook, pp. 1189-1196,
edited by R.C. Dorf, CRC Press & IEEE Press, 1996.

B.C. Rothenberg, S.H. Lewis, and P.J. Hurst, "A 20 MSample/s Switched-Capacitor Finite-
Impulse-Response Filter Using a Transposed Structure," IEEE J. of Solid-State Circuits, pp.
1350-1356, Dec. 1995.

P.J. Hurst and S.H. Lewis,
"Determination of Stability Using Return Ratios in Balanced Fully
Differential Feedback Circuits,"
IEEE Trans. on Circuits and Systems II, pp. 805-817, December 1995.

(FTP information for the example described in Section VI)

P. Roo, R.R. Spencer and P.J. Hurst, "Analog timing recovery architectures for PRML
detectors," Globecom Conference Record, Singapore, Vol. 1, pp 571-576, Nov. 1995.

J.E. Brown and P.J. Hurst, 'An adaptive continuous-time forward equalizer for a DFE-
based disk-drive read channel," Asilomar Conference on Signals, Systems, and Computers,
Pacific Grove/Monterey, Vol. 1, pp. 668-672, Oct., 1995.

S.K. Berg, P.J. Hurst and S.H. Lewis, "An 80 MSample/s Video Switched-Capacitor
Filter using a Parallel Biquadratic Structure," IEEE Journal of Solid-State Circuits, vol.
30, no. 8, pp. 898-905, August 1995.

T.V. Burmas, S.H. Lewis, P.J. Hurst and K. Dyer, "A Second-Order Double-Sampled
Delta-Sigma Modulator," IEEE Custom Integrated Circuits Conf., Santa Clara, pp. 195-
198, May 1995.

J.E.C. Brown, P.J. Hurst and L. Der, "A 35 Mb/s Mixed-Signal Decision-Feedback
Equalizer for Disk-Drive Applications," IEEE Custom IC Conf., Santa Clara, pp. 563-
566, May 1995.

P.J. Hurst and B.C. Rothenberg, "A Clock Generator Using Noise Shaping and Its
Application in Switched-Capacitor Filters," IEEE Journal of Solid-State Circuits,
vol. 30, no. 4, pp. 403-411, April 1995.

B.C. Rothenberg, S.H. Lewis and P.J. Hurst, "A 20 MSample/s Switched-Capacitor
Finite-Impulse-Response Filter in 2µm CMOS," IEEE International Solid-State Circuits
Conference, San Francisco, pp. 210-211 and 369, February 1995.

R.S. Kajley, P.J. Hurst, and J.E.C. Brown, "A Mixed-Signal Decision-Feedback
Equalizer Using a Look-Ahead Architecture," IEEE Asilomar Conf. on Signals, Systems,
and Computers, Asilomar, pp. 1413-1417, Oct. 1994.

J.E.C. Brown, P.J. Hurst, I. Agi and L. Der, "Analog Decision-Feedback Equalizer
Architectures," IEEE VLSI Signal Processing Workshop, La Jolla, pp. 266-275, Oct.
1994.

P.J. Hurst and B.C. Rothenberg, "A Clock Generator Using Noise Shaping and Its
Application in a Switched-Capacitor Filter," IEEE & JSAP Symposium on VLSI Circuits,
Honolulu, pp. 105-106, June 1994.

J.E.C. Brown, P.J. Hurst, L. Der and I. Agi, "A Comparison of Analog Decision-
Feedback Equalizer Architectures," IEEE International Symposium on Circuits and
Systems, London, vol. 4, pp. 99-102, May 1994.

P.J. Hurst and S.H. Lewis, "Simulation of Return Ratio in Fully Differential Circuits,"
IEEE Custom Integrated Circuits Conf., San Diego, pp. 29-32, May 1994.

S.K. Berg, P.J. Hurst, S.H. Lewis and P.T. Wong, "A Switched-Capacitor Filter in 2 µm
CMOS using Parallelism to Sample at 80 MHz," IEEE International Solid-State Circuits
Conference, San Francisco, pp. 62-63 and 311, February 1994.

L. Der, S.H. Lewis and P.J. Hurst, "A Switched-Capacitor Differencing Circuit with
Common-Mode Rejection for Fully Differential Comparators," Midwest Symp. on
Circuits and Systems, Detroit, pp. 911-914, August 1993.

P.J. Hurst, R.A. Levinson and D.J. Block, "A Switched-Capacitor Delta-Sigma
Modulator with Reduced Sensitivity to Op Amp Gain," IEEE Journal of Solid-State
Circuits, vol. 28, no. 3, pp. 691-696, June 1993.

I. Agi, P.J. Hurst and K.W. Current. "An Image Processing IC for Backprojection and
Spatial Histogramming in a Pipelined Array," IEEE Journal of Solid-State Circuits, vol.
28, no. 3, pp. 210-221, March 1993.

E. Shieh, K.W. Current, P.J. Hurst and I. Agi. "High-Speed Computation of the Radon
Transform and Backprojection Using an Expandable Multiprocessor Architecture," IEEE
Transactions on Circuits and Systems for Video Technology, pp. 347-360, December
1992.

I. Agi, P.J. Hurst and K.W. Current. "An Expandable Computed Tomography
Architecture for Non-destructive Evaluation," SPIE Symposium on Applications of
Signal and Image Processing in Explosives Detection Systems, Vol. 1824, pp. 41-52,
November 1992.

J.E. Brown, P.J. Hurst and L. Der. "Design of an Analog DFE for Disk-Drive
Applications," IEEE Asilomar Conf. on Signals, Systems, and Computers, pp. 965-969,
October 1992.

P.J. Hurst,
"A Comparison of Two Approaches to Feedback Circuit Analysis,"
IEEE Trans. on Education, vol. 35, no. 3, pp. 253-261, August 1992.

I. Agi, P.J. Hurst and K.W. Current. "A Pipelined VLSI Chip Architecture for Real-Time
Computed Tomography of Fan-Beam Data," IEEE International Symposium on Circuits
and Systems, pp. 661-664, May 1992.

P.J. Hurst and K.C. Dyer. "An Improved Double-Sampling Scheme for Switched-
Capacitor Delta-Sigma Modulators," IEEE International Symposium on Circuits and
Systems, pp. 1179-1182, May 1992.

I. Agi, P.J. Hurst and K.W. Current. "A 450 MOPS Image Backprojector and
Histogrammer," IEEE Custom Integrated Circuits Conf., pp. 6.2.1-6.2.4, May 1992.

I. Agi, P.J. Hurst, and A.K. Jain. "A VLSI Processor for Parallel Contour Tracing," IEEE
Trans. on Signal Processing, pp. 429-438, vol. 40, no. 2, Feb. 1992.

R.R. Spencer and P.J. Hurst. "Analog Implementations of Sampling Detectors," IEEE
Trans. on Magnetics, pp. 4516-4521, vol. 27, no. 6, Nov. 1991.

P.J. Hurst,
"Exact Simulation of Feedback Circuit Parameters,"
IEEE Trans. on Circuits and Systems,
vol. 38, no. 11, pp. 1382-1389, Nov. 1991.

P.J. Hurst and J.E. Brown. "Finite Impulse Response Switched-Capacitor Filters for the
Delta-Sigma Modulator D/A Interface," IEEE Trans. on Circuits and Systems, vol. 38,
no. 11, pp. 1391-1397, Nov. 1991.

R.R. Spencer and P.J. Hurst. "Analog Implementations of Sampling Detectors," Digest of
the Magnetic Recording Conf., Pittsburg, pp. B5-B5 (2 pages), June 1991.

P.J. Hurst. "Shifting the Frequency Response of Switched-Capacitor Filters by
Nonuniform Sampling," IEEE Trans. on Circuits and Systems, vol. 38, no. 1, pp. 12-19,
Jan. 1991.

I. Agi, P.J. Hurst, and K.W. Current. "A Pipelined IC Architecture for Radon Transform
Computations in a Multiprocessor Array," IEEE Workshop on VLSI Signal Processing,
San Diego, pp. 442-451, Nov. 1990.

S.D. Levy, P.J. Hurst, P. Ju, J.M. Huggins, and C.R. Cole. "A Single-Chip
5-V 2400 BPS Modem," IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 632-
643, June 1990.

K.W. Current, P.J. Hurst, E. Shieh, and I. Agi. "An Evaluation of Radon Transform
Computations using DSP Chips," Journal on Machine Vision and Applications, no. 3, pp.
63-74, 1990.

P.J. Hurst and W.J. McIntyre. "Double Sampling in Switched-Capacitor DSM A/Ds,"
IEEE International Symposium on Circuits and Systems, pp. 902-905, May 1990.

E. Shieh, K.W. Current, P.J. Hurst, and I. Agi. "A High Speed Radon Transform and
Backprojection Processor," IEEE International Symposium on Circuits and Systems, pp.
234-237, May 1990.

P.J. Hurst, K.W. Current, I. Agi, and E. Shieh. "A VLSI Architecture for Two-
Dimensional Radon Transform Computation," IEEE International Conference on
Acoustics, Speech and Signal Processing, Albuquerque, pp. 933-936, April 1990.

I. Agi, P.J. Hurst, K.W. Current, E. Shieh, S. Azevedo and G. Ford. "A VLSI
Architecture for High-Speed Image Reconstruction: Considerations for a Fixed-Point
Architecture," SPIE Symposium on Electronic Imaging, Santa Clara, pp. 11-24, February
1990.

S.D. Levy, P.J. Hurst, P. Ju, J.M. Huggins, and C.R. Cole, "A Single-Chip 5-V 2400bps
Modem," Proc. of the European Solid-State Circuits Conf. , Vienna, pp. 188-191,
September 1989.

S.B. Haley and P.J. Hurst, "Accurate Pole and Zero Approximations for Linear Circuits,"
IEEE Trans. on Circuits and Systems , vol. 36, no. 6, pp. 838-845, June 1989. S.B. Haley
and P.J. Hurst, "Errata in 'Accurate Pole and Zero Approximations for Linear Circuits',"
IEEE Trans. on Circuits and Systems, vol. 38, no. 11, p. 1406, Nov. 1991.

P.J. Hurst and R.A. Levinson, "Delta-Sigma A/Ds with Reduced Sensitivity to Op Amp
Noise and Gain," IEEE Int'l Symposium on Circuits and Systems, Portland, pp. 254-257,
May 1989. Reprinted in Oversampling Delta-Sigma Data Converters, IEEE Press, 1992.

P.J. Hurst and J.E.C. Brown, "Finite Impulse Response Switched-Capacitor Decimation
Filters for the DSM D/A Interface," IEEE Int'l Symposium on Circuits and Systems,
Portland, pp. 1688-1691, May 1989.

E. Shieh, W. Current, P. Hurst, and I. Agi, "Radon Transform Computations using DSP
Chips - An Evaluation and Comparison," IEEE Int'l Symposium on Circuits and Systems,
Portland, pp. 1899-1902, May 1989.

S.G. Azevedo, A.J. DeGroot, H.E. Martz, A.K. Jain, K.W. Current, and P.J. Hurst, "A
Radon Transform Computer for Multidimensional Signal Processing," Int'l Conf. on
Acoustics, Speech, and Signal Processing, Glasgow, Scotland, pp. 1457-1459, May 1989.

I. Agi, P.J. Hurst, and A.K. Jain, "A Processor for Fast Contour Tracing," in VLSI Signal
Processing III, IEEE Press, pp. 129-141, November 1988.

S.G. Azevedo, A.J. DeGroot, D.J. Schneberk, J.M. Brase, H.E. Martz, A.K. Jain, K.W.
Current, and P.J. Hurst, "Tomographic Image Reconstruction using Systolic Array
Algorithms," in D.O. Thompson and D.E. Chiminti, editors, Review in Progress in
Quantitative Non-Destructive Evaluation, vol. 8A, La Jolla, pp. 415-422, August 1988.

P.J. Hurst, T.J. Glad, J.J. Illgner, and G.F. Landsburg, "An Analog Front End for V.22bis
Modems," IEEE Journal of Solid-State Circuits, vol. SC-23, no. 4, pp. 978-986, August
1988.

I. Agi, P.J. Hurst, and A.K. Jain, "An Expandable VLSI Processor Array Approach to
Contour Tracing," Int. Conf. on Acoustics, Speech, and Signal Processing, New York, pp.
1969-1972, April 1988.

P.J. Hurst, T.J. Glad, J.J. Illgner, and G.F. Landsburg, "An Analog Front End for V.22bis
Modems," Proc. of the Custom Integrated Circuits Conference, Portland, pp. 449-452,
May 1987.

M.W. Hauser, P.J. Hurst, and R.W. Brodersen, "An MOS ADC-Filter Combination That
Does Not Require Precision Analog Components," Digest of the International Solid-
State Circuits Conference, New York, pp. 80-81 and 313, February 1985. Reprinted in
Analog MOS Integrated Circuits, II, IEEE Press, 1989. Reprinted in Oversampling
Delta-Sigma Data Converters, IEEE Press, 1992. Reprinted in 40-Year Commemorative
Supplement to the Digest of the International Solid-State Circuits Conf., pp. 46-47 and
145, 1993.

P.J. Hurst and R.W. Brodersen, "An MOS-LSI Autocorrelator for Linear Prediction of
Speech," IEEE Journal of Solid-State Circuits, vol. SC-19, no. 6, pp. 1022-1029,
December 1984.

P.J. Hurst, "An MOS-LSI Autocorrelation Linear Prediction System," U.C. Berkeley,
Dept. of Electrical Engineering, ERL Memo No. UCB/ERL/M83/51, August 1983.

R.D. Fellman, P.J. Hurst, and R.W. Brodersen, "Switched-Capacitor Circuits for
Adaptive Filtering and Autocorrelation," Digest of the International Solid-State Circuits
Conference, New York, pp. 126-127, February 1983.

R.D. Fellman, P.J. Hurst, and R.W. Brodersen, "MOS-LSI Analog/Digital Techniques for
Linear Prediction," Proc. of the International Conf. on Communication, Seattle, pp.
57.1.1-57.1.5, June 1980.

R.W. Brodersen, P.J. Hurst, and D. Allstot, "Switched-Capacitor Applications in Speech
Processing," International Symposium on Circuits and Systems, Dallas, pp. 732-737,
April 1980.

R.W. Brodersen, P.J. Hurst, D.J. Allstot, and T. Tsuda, "Switched-Capacitor Applications
in Speech Processing," Proc. of Case Studies in Advanced Signal Processing, IEE Conf.
Publication No. 180, pp. 14-19, Peebles, Scotland, Sept. 1979.

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