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Welcome to ASEEC Lab

The Accelerated, Secure, and Energy-Efficient Computing Lab (ASEEC), in the Electrical and Computer Engineering Department of the George Mason University, under the direction of Dr. Houman Homayoun, is a center for the investigation of Secure, Energy-Efficient, and High Performance Computer Architecture Design. The group pursues experimental research in the areas of big data computing, hardware security and trust, hardware accelerator for machine learning analytics, heterogeneous architecture design, developing energy-efficient algorithms for emerging big data applications, accelerating big data computing, emerging memory technologies for big data, and mapping and scheduling applications into heterogeneous architectures.

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NEWS!

    2021

  • July, Nadir Amin Carreon Rascon joins ASEEC lab as a postdoc fellow
  • May, Three projects total of $250K/year funded by CHEST industry sponsors
  • February, Two new projects total of $425K/year funded by Noyce Foundation
  • January, Three papers accepted in DAC 2021
  • 2020

  • November, ASEEC lab received best paper award at 14th IEEE DCAS 2020
  • November, Houman Homayoun gave a keynote talk at 14th IEEE DCAS
  • September, Soheil Salehi join ASEEC lab as NSF CI Fellow
  • July, Best paper nominee at IEEE ISVLSI 2020
  • June, NSF RAPID program funds ASEEC lab project on understanding malware epidemics for better policy guiding
  • May, Houman Homayoun received 2020 ACM GLSVLSI Service Recognition Award
  • March, Houman Homayoun is now IEEE senior member
  • 2019

  • January, two papers on hardware security and obfuscation, and adversarial machine learning accepted in DAC 2019
  • 2018

  • December, Arezou Koohi successfully defended her PhD dissertations
  • October, Jeremy Muldavin from DoD OSD visited ECE department and ASEEC lab
  • October, two papers on IoT security and malware detection accepted in DATE 2019
  • September, SMT attack accepted in CHES 2019 August, Maria Malik and Katayoun Neshatpour successfully defended their dissertations. Maria joined Intel, and Katayoun joined Cadence
  • August, A successful Planning Grant Meeting of NSF Center for Hardware and Embedded Systems Security and Trust (CHEST) @ GMU, 100+ participants from 6 member universities, more than 30 government research labs and lead industries in cybersecurity
  • May, Maria Malik received 2018 ECE Department Outstanding Academic Achievement Award
  • July, Member of Advisory Committee, Cybersecurity Research and Technology Commercialization (R&TC) working group, Commonwealth of Virginia
  • July, Special session on Adversarial Machine Learning at ICCAD 2018
  • July, Invited talk on machine learning acceleration at ASPDAC 2019
  • August, Several papers accepted in ASPDAC, SoCC, CHES, FCCM, MEMSYS, ASAP, and CGRID 2018
  • July, Two journals on HW security and IoT accepted in TODAES Special issue on Internet of Things System Performance, Reliability, and Security
  • July, Two journals on big data computing topic accepted in TOMPECS and TMSCS
  • June, Serving in advisory Committee, Research and Technology Commercialization (R&TC), Cybersecurity working group, Commonwealth of Virginia
  • March, paper on design space exploration of mapreduce accepted in FCCM 2018
  • February, paper on ensemble learning malware detection accepted in DAC 2018
  • 2017

  • December, NSF funded planning IUCRC GMU: Center for Hardware and Embedded System Security and Trust (CHEST), will be serving as PI
  • December, Katayoun Neshatpour, PhD student at ASEEC lab will be joining Cadence in Spring 2018
  • December, Professor Jack Sampson from Penn State visited ASEEC lab
  • November, ICNN paper: An Iterative Implementation of Convolutional Neural Networks accepted in DATE 2018
  • October, Sai Manoj Pudukotai DinakarRao joined us as postdoc from TU Wien
  • October, Professor Walid Najjar from UCR visited ASEEC lab
  • October, Serving as TPC member for HOST, DAC, and IPDPS 2018
  • October, Professor Sandip Kundu from NSF/UMass Amherst visited ASEEC lab
  • September, Serving as TPC program Co-Chair for GLSVLSI 2018 in Chicago!
  • September, paper on scheduling multithreaded applications to composite cores accepted in ICCD 2017
  • September, paper on power conversion efficiency aware task scheduling in heterogeneous architectures accepted in ASPDAC 2018
  • September, 6 journals accepted in TVLSI (4), TMSCS, and JETC
  • September, a new project recommended for funding by DARPA on Developing Machine Learning Algorithms for Detecting Malware
  • August, 4 new PhD students joined ASEEC lab
  • August, 6 new MS students joined ASEEC lab to work towards thesis
  • August, A new exciting project by NSF-CNS on accelerating convolutional neural networks
  • August, 3 papers accepted in IISWC 2017 on DRAM for big data, co-scheduling big data applications, and system level modeling for cloud architectures
  • July, An invited paper and talk on memory requirements of big data at IGSC 2017 conference
  • June, New exciting project recommended for funding by DARPA on 3D-Split of Obfuscation and Authentication of logic
  • May, Paper on big data acceleration and compressed sensing accepted in TECS
  • May, Paper on Reformulation of Peak Current Reduction accepted in ISLPED 2017
  • March, A new exciting project on hardware security proof of concept in 14nm
  • March, Journal on voltage regulator design accepted in TVLSI
  • February, Paper on hardware performance counter for security accepted in DAC 2017
  • February, Serving as TPC member for ICCD 2017. February, Congrats to Maria for receiving provost summer fellowship
  • January, Serving on CASES and CODES ISSS TPC
  • 2016

  • December, Serving as an Associate Editor for Transactions on VLSI
  • November, Two papers on big data computing accepted in DATE 2017 conference
  • October, Serving as TPC member for HOST, DAC, DATE, and CF
  • September, Patent on logical vanishable design to prevent reverse engineering
  • July, Organizing a special session on heterogeneous architectures and big data in CODES-ISSS 2016
  • May, Maria joined Intel for summer intern. Katayoun joined USC ISI for summer intern
  • May, Received the Best Paper award of GLSVLSI 2016 on heterogeneous accelerator for wearable biomedical computing
  • May, Presenting an invited talk on heterogeneous architecture and big data in computing frontiers 2016
  • May, Visited KIT and gave a talk on accelerating big data analytics
  • May, Visited Politecnico Di Milano and gave a talk on heterogeneous architectures for big data
  • May, Visited TU Dresden and gave a talk on accelerating big data analytics
  • April, Paper on embedded vision processing accepted in ISVLSI 2016
  • March, Paper on reconfigurable logic accepted in ICCD 2016
  • February, Paper on STT-CMOS Hybrid Designs for Reverse-engineering Prevention accepted in DAC 2016 conference
  • January, Paper on Characterizing Hadoop Applications on Microservers accepted in ISPASS 2016
  • 2015

  • October, Long Paper on Hadoop Big Data Acceleration Presented at IEEE Big Data
  • October, Long Paper on Big Vs Little Core for Hadoop Kernels Presented in IEEE Big Data
  • October, Paper on Big Data Characterization on Little Core Presented at ICCD 2015
  • October, Paper on Tuning Edge Detection on Commodity Embedded Platforms Presented at ICCD
  • October, Paper on Wide I/O vs HMC presented at ICCD 2015
  • October, Serving on ISPASS 2016 TPC
  • October, Paper on Manycore On Chip Power Delivery Presented at ICCD 2015
  • October, Serving on DAC 2016 TPC
  • October, $288K Grant from NSF CNS to Study Heterogeneous Architecture Design for Emerging Wearable Biomedical Applications
  • September, $330K Grant from DARPA to study Reconfigurable STT LUT Logic to Improve Power Efficiency
  • September, Two Papers Accepted at IEEE Big Data 2015
  • September, Four New PhD Students Joined ASEEC Lab
  • July, Four Papers Accepted at ICCD 2015
  • March, Paper on Big Data Acceleration Using FPGAs accepted in FCCM 2015
  • March, Paper accepted in Computing Frontiers 2015
  • March, Paper on Hadoop Acceleration using ZYNQ accepted in CCGRID 2015
  • February, Paper on dynamic heterogeneity accepted in DAC 2015
  • February, Paper on 3D HMC Memory Management accepted in GLSVLSI 2015
  • February, Paper on Inverse Thermal Dependant accepted in GLSVLSI 2015
  • October, Serving on DAC 2015 Embedded Systems Track TPC
  • October, Invited Talk at IBM TJ Watson on Big Data Computing
  • September, Congrats to Maria, Katayoun and Mohammad for passing the PhD qualifying exam
  • July, Paper on Phase Change Material Modeling for Temperature Management accepted in ICCD 2014
  • June, Invited paper on Enabling Dynamic Heterogeneity Through Core on Core Stacking in DAC 2014
  • June, Paper on Hybrid STT-RAM Cache accepted in IGCC 2014
  • April, Paper on Mapping Biomedical Applications to Many-core accelerators accepted in ISLPED 2014
  • January, Organizing a special session on Heterogeneous Architectures, Accelerators, Tools, and Workloads in DAC 2014 Conference
  • 2014

  • November, Adarsh's Paper on Non-volatile Logic Accepted at DATE conference
  • November, I am Presenting a Tutorial on Dynamic Heterogeneous Architecture in DATE conference
  • October, Paper on Probabilistic Write for STT-RAMs presented at ICCD 2013 conference
  • September, we have 6 new PhD-student lab members!
  • August, $995K award from NSF Cyber Physical System program
  • July, $261K award from General Motors for Security Project
  • June, Paper on Resistive Computation: A Critique accepted at computer architecture letter
  • June, Tutorial on Dynamic Heterogeneous Architecture will be presented at DAC 2013
  • May, Keynote talk on Future of Heterogeneous Architecture at United States Patent and Trademark Office (USPTO)
  • May, Paper on Reliability in NUCA cache accepted at IGCC 2013
  • March, Invited talk at Virgina Tech Center for Embedded Systems for Critical Applications (CESCA)
  • February, Paper on 3D multicore lifetime reliability accepted at DAC 2013
  • September, paper on Heterogeneous 3D DRAM accepted at ASP-DAC 2013
  • February, Paper Accepted at ISCA 2012
  • February, Tutorial on System-Level Exploration of Power, Temperature, and Performance accepted at DAC 2012
  • 2013

  • December, Serving on the TPC of ISLPED 2012
  • December, Serving on the TPC of 2011 ACM conference of Computing Frontiers
  • December, Serving on the TPC of 2011 IEEE-ISQED
  • November, Paper on "3D Heterogeneous Cores" Accepted at HPCA 2012
  • November, Paper on "Inquisitive Defect Cache" appeared in TVLSI
  • November, Paper on "MZZ-HVS peripherals" appeared in TVLSI
  • November, Paper on "Centralized Power Management" appeared in TVLSI
  • November, Paper on "Hot Peripheral Thermal Management" Accepted at ISQED 2012
  • November, Paper on "History & Variation Trained Cache" Accepted at ISQED 2012
  • November, Invited talk on "Flexible Fault-Tolerant Cache Architecture" at 2011 SOC Conference
  • November, Doctoral Dissertation nominated for ACM Dissertation award
  • November, talk on "multiple sleep modes design" at Arizona State University
  • November, Invited talk on "resource adaptation for power management" at 2010 SOC Conference
  • November, Paper on "multi copy cache architecture for reliability" appeared in CASES 2010
  • October, Serving on the TPC of 2012 IEEE-ISQED
  • October, Paper on "FFT-Cache" appeared in CASES 2011
  • October, Paper on "Reliability-Aware Placement in SRAM-based FPGA" appeared in CODES-ISSS 2011
  • September, Serving on the TPC of 2011 IEEE-AICCSA
  • September, paper on "multiple sleep mode design" accepted in TVLSI