Self-Aligned Gate MOSFET
- 1. R. W. Bower. FIELD-EFFECT DEVICE WITH INSULATED GATE. Patent, U.S. 3,472,712, issued October 14, 1969.
- 2. R. W. Bower. INSULATED-GATE FIELD-EFFECT DEVICE HAVING SOURCE AND DRAIN REGIONS FORMED IN PART BY ION IMPLANTATION AND METHOD OF MAKING SAME. Patent, U.S. 3,615,934, issued October 26, 1971.
- These two patent describe the Self-Aligned Gate MOSFET
These 2 patents are the base of the self-aligned gate MOSFET concept.
A MOSFET is a simple switch with a control element called a gate that must span the space separating the source and drain (this space is called the channel) to form a conductive bridge that closes the switch and allows current to flow from source to drain.
The patent replaced the standard procedure of
- 1. Forming a Source and Drain first.
- 2. Then forming a gate insulator
- 3. And finally the gate is placed on the structure. This gate must be made approximately 3 times larger than the space between the source and drain to insure that this whole region is spanned.
- 4. This results in a slow device the characteristics of which are strongly affected by the random misalignment of this gate element.
- 5. This means that MOSFET circuits are not only slow, but the circuits must be designed so they still function with the worst case random misalignment of the gate over the source and drain. This causes the circuits to be even slower than the 3 times larger gate would predict.
The Self-Aligned Gate MOSFET invented by Bower forms the device in the following manner.
- 1. Form the gate insulator first.
- 2. Then form a gate that has a size that is precisely that of the desired spacing that will separate the source and drain because!
- 3. The gate itself is used as the mask that establishes the source and drain. Thus, the source and drain automatically are exactly aligned precisely where they should be and the gate is just the size required to cover the channel region.
- 4. Thus, the device is fast because the gate is 3 times smaller, and circuits designed with this device so the circuits can be designed at full speed without the uncertainty factor related to random gate misalignment.