Analysis & Synthesis report for vga_top
Tue May 03 00:19:54 2022
Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for User Entity Instance: VGA_controller:vga_control
 12. Port Connectivity Checks: "VGA_controller:vga_control"
 13. Post-Synthesis Netlist Statistics for Top Partition
 14. Elapsed Time Per Partition
 15. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2020  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status     ; Successful - Tue May 03 00:19:54 2022           ;
; Quartus Prime Version           ; 20.1.0 Build 711 06/05/2020 SJ Standard Edition ;
; Revision Name                   ; vga_top                                         ;
; Top-level Entity Name           ; vga_top                                         ;
; Family                          ; Cyclone V                                       ;
; Logic utilization (in ALMs)     ; N/A                                             ;
; Total registers                 ; 88                                              ;
; Total pins                      ; 102                                             ;
; Total virtual pins              ; 0                                               ;
; Total block memory bits         ; 0                                               ;
; Total DSP Blocks                ; 0                                               ;
; Total HSSI RX PCSs              ; 0                                               ;
; Total HSSI PMA RX Deserializers ; 0                                               ;
; Total HSSI TX PCSs              ; 0                                               ;
; Total HSSI PMA TX Serializers   ; 0                                               ;
; Total PLLs                      ; 0                                               ;
; Total DLLs                      ; 0                                               ;
+---------------------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
; Top-level entity name                                                           ; vga_top            ; vga_top            ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                 ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                   ; Library ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+
; VGA_controller.v                 ; yes             ; User Verilog HDL File  ; C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v ;         ;
; VGA_Param.h                      ; yes             ; User File              ; C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_Param.h      ;         ;
; vga_top.v                        ; yes             ; User Verilog HDL File  ; C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v        ;         ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+---------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimate of Logic utilization (ALMs needed) ; 61      ;
;                                             ;         ;
; Combinational ALUT usage for logic          ; 106     ;
;     -- 7 input functions                    ; 0       ;
;     -- 6 input functions                    ; 14      ;
;     -- 5 input functions                    ; 8       ;
;     -- 4 input functions                    ; 12      ;
;     -- <=3 input functions                  ; 72      ;
;                                             ;         ;
; Dedicated logic registers                   ; 88      ;
;                                             ;         ;
; I/O pins                                    ; 102     ;
;                                             ;         ;
; Total DSP Blocks                            ; 0       ;
;                                             ;         ;
; Maximum fan-out node                        ; rClk[0] ;
; Maximum fan-out                             ; 89      ;
; Total fan-out                               ; 727     ;
; Average fan-out                             ; 1.83    ;
+---------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                            ;
+---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------------------+----------------+--------------+
; Compilation Hierarchy Node      ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                 ; Entity Name    ; Library Name ;
+---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------------------+----------------+--------------+
; |vga_top                        ; 106 (28)            ; 88 (9)                    ; 0                 ; 0          ; 102  ; 0            ; |vga_top                            ; vga_top        ; work         ;
;    |VGA_controller:vga_control| ; 78 (78)             ; 79 (79)                   ; 0                 ; 0          ; 0    ; 0            ; |vga_top|VGA_controller:vga_control ; VGA_controller ; work         ;
+---------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-------------------------------------+----------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; VGA_controller:vga_control|ovga_sync   ; Stuck at GND due to stuck port data_in ;
; red[1,4,5,7]                           ; Merged with red[0]                     ;
; red[3,6]                               ; Merged with red[2]                     ;
; green[5..7]                            ; Merged with green[2]                   ;
; green[4]                               ; Merged with green[3]                   ;
; blue[1..3]                             ; Merged with blue[0]                    ;
; blue[5..7]                             ; Merged with blue[4]                    ;
; rClk[1]                                ; Lost fanout                            ;
; VGA_controller:vga_control|col[0,1]    ; Lost fanout                            ;
; Total Number of Removed Registers = 20 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 88    ;
; Number of registers using Synchronous Clear  ; 26    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 55    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 21    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |vga_top|green_c           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_controller:vga_control ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; H_SYNC_CYC     ; 96    ; Signed Integer                                 ;
; H_SYNC_BACK    ; 48    ; Signed Integer                                 ;
; H_SYNC_ACT     ; 640   ; Signed Integer                                 ;
; H_SYNC_FRONT   ; 16    ; Signed Integer                                 ;
; H_SYNC_TOTAL   ; 800   ; Signed Integer                                 ;
; V_SYNC_CYC     ; 2     ; Signed Integer                                 ;
; V_SYNC_BACK    ; 33    ; Signed Integer                                 ;
; V_SYNC_ACT     ; 480   ; Signed Integer                                 ;
; V_SYNC_FRONT   ; 10    ; Signed Integer                                 ;
; V_SYNC_TOTAL   ; 525   ; Signed Integer                                 ;
; X_START        ; 144   ; Signed Integer                                 ;
; Y_START        ; 35    ; Signed Integer                                 ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "VGA_controller:vga_control"                                                                                                        ;
+--------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                                                                    ;
+--------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------+
; orequest     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                        ;
; ired[9..8]   ; Input  ; Info     ; Stuck at GND                                                                                                               ;
; igreen[9..8] ; Input  ; Info     ; Stuck at GND                                                                                                               ;
; iblue[9..8]  ; Input  ; Info     ; Stuck at GND                                                                                                               ;
; ored         ; Output ; Warning  ; Output or bidir port (10 bits) is wider than the port expression (8 bits) it drives; bit(s) "ored[9..8]" have no fanouts   ;
; ogreen       ; Output ; Warning  ; Output or bidir port (10 bits) is wider than the port expression (8 bits) it drives; bit(s) "ogreen[9..8]" have no fanouts ;
; oblue        ; Output ; Warning  ; Output or bidir port (10 bits) is wider than the port expression (8 bits) it drives; bit(s) "oblue[9..8]" have no fanouts  ;
+--------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; arriav_ff             ; 88                          ;
;     CLR               ; 29                          ;
;     CLR SCLR          ; 13                          ;
;     ENA               ; 8                           ;
;     ENA CLR SCLR      ; 13                          ;
;     plain             ; 25                          ;
; arriav_lcell_comb     ; 108                         ;
;     arith             ; 51                          ;
;         1 data inputs ; 50                          ;
;         2 data inputs ; 1                           ;
;     normal            ; 57                          ;
;         0 data inputs ; 1                           ;
;         1 data inputs ; 2                           ;
;         2 data inputs ; 15                          ;
;         3 data inputs ; 5                           ;
;         4 data inputs ; 12                          ;
;         5 data inputs ; 8                           ;
;         6 data inputs ; 14                          ;
; boundary_port         ; 102                         ;
;                       ;                             ;
; Max LUT depth         ; 4.00                        ;
; Average LUT depth     ; 2.20                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition
    Info: Processing started: Tue May 03 00:19:40 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_top -c vga_top
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file vga_controller.v
    Info (12023): Found entity 1: VGA_controller File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 43
Warning (10275): Verilog HDL Module Instantiation warning at vga_top.v(186): ignored dangling comma in List of Port Connections File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 186
Info (12021): Found 1 design units, including 1 entities, in source file vga_top.v
    Info (12023): Found entity 1: vga_top File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 9
Info (12127): Elaborating entity "vga_top" for the top level hierarchy
Warning (10034): Output port "LEDR[9..1]" at vga_top.v(51) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
Warning (10034): Output port "HEX0[7..1]" at vga_top.v(54) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
Warning (10034): Output port "HEX1" at vga_top.v(55) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
Warning (10034): Output port "HEX2" at vga_top.v(56) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
Warning (10034): Output port "HEX3" at vga_top.v(57) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
Warning (10034): Output port "HEX4" at vga_top.v(58) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
Warning (10034): Output port "HEX5" at vga_top.v(59) has no driver File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
Info (12128): Elaborating entity "VGA_controller" for hierarchy "VGA_controller:vga_control" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 186
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(111): truncated value with size 32 to match size of target (10) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 111
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(114): truncated value with size 32 to match size of target (10) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 114
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(117): truncated value with size 32 to match size of target (10) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 117
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(123): truncated value with size 32 to match size of target (13) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 123
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(124): truncated value with size 32 to match size of target (13) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 124
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(181): truncated value with size 32 to match size of target (13) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 181
Warning (10230): Verilog HDL assignment warning at VGA_controller.v(207): truncated value with size 32 to match size of target (13) File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v Line: 207
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "LEDR[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[8]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "LEDR[9]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 51
    Warning (13410): Pin "HEX0[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX0[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX0[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX0[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX0[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX0[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX0[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 54
    Warning (13410): Pin "HEX1[0]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX1[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 55
    Warning (13410): Pin "HEX2[0]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX2[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 56
    Warning (13410): Pin "HEX3[0]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX3[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 57
    Warning (13410): Pin "HEX4[0]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX4[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 58
    Warning (13410): Pin "HEX5[0]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[1]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[2]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[3]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[4]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[5]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[6]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "HEX5[7]" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 59
    Warning (13410): Pin "VGA_SYNC_N" is stuck at GND File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 67
Info (286030): Timing-Driven Synthesis is running
Info (17049): 3 registers lost all their fanouts during netlist optimizations.
Warning (20013): Ignored 24 assignments for entity "vga" -- entity does not exist in design
    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity vga -section_id Top was ignored
    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity vga -section_id Top was ignored
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 11 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 48
    Warning (15610): No output dependent on input pin "KEY[2]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 48
    Warning (15610): No output dependent on input pin "SW[0]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[1]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[2]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[3]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[4]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[5]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[6]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[7]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
    Warning (15610): No output dependent on input pin "SW[8]" File: C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v Line: 45
Info (21057): Implemented 232 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 15 input pins
    Info (21059): Implemented 87 output pins
    Info (21061): Implemented 130 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 112 warnings
    Info: Peak virtual memory: 4830 megabytes
    Info: Processing ended: Tue May 03 00:19:54 2022
    Info: Elapsed time: 00:00:14
    Info: Total CPU time (on all processors): 00:00:35


