{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1651562315237 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1651562315238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 03 00:18:34 2022 " "Processing started: Tue May 03 00:18:34 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1651562315238 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1651562315238 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_top -c vga_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off vga_top -c vga_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1651562315238 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1651562315981 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1651562315981 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file vga_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_controller " "Found entity 1: VGA_controller" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1651562327337 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1651562327337 ""}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "vga_top.v(186) " "Verilog HDL Module Instantiation warning at vga_top.v(186): ignored dangling comma in List of Port Connections" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 186 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "Analysis & Synthesis" 0 -1 1651562327337 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_top.v 1 1 " "Found 1 design units, including 1 entities, in source file vga_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_top " "Found entity 1: vga_top" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1651562327337 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1651562327337 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga_top " "Elaborating entity \"vga_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1651562327393 ""}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[9..1\] vga_top.v(51) " "Output port \"LEDR\[9..1\]\" at vga_top.v(51) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX0\[7..1\] vga_top.v(54) " "Output port \"HEX0\[7..1\]\" at vga_top.v(54) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX1 vga_top.v(55) " "Output port \"HEX1\" at vga_top.v(55) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2 vga_top.v(56) " "Output port \"HEX2\" at vga_top.v(56) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3 vga_top.v(57) " "Output port \"HEX3\" at vga_top.v(57) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX4 vga_top.v(58) " "Output port \"HEX4\" at vga_top.v(58) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX5 vga_top.v(59) " "Output port \"HEX5\" at vga_top.v(59) has no driver" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1651562327396 "|vga_top"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_controller VGA_controller:vga_control " "Elaborating entity \"VGA_controller\" for hierarchy \"VGA_controller:vga_control\"" {  } { { "vga_top.v" "vga_control" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 186 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_controller.v(111) " "Verilog HDL assignment warning at VGA_controller.v(111): truncated value with size 32 to match size of target (10)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_controller.v(114) " "Verilog HDL assignment warning at VGA_controller.v(114): truncated value with size 32 to match size of target (10)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_controller.v(117) " "Verilog HDL assignment warning at VGA_controller.v(117): truncated value with size 32 to match size of target (10)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 VGA_controller.v(123) " "Verilog HDL assignment warning at VGA_controller.v(123): truncated value with size 32 to match size of target (13)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 VGA_controller.v(124) " "Verilog HDL assignment warning at VGA_controller.v(124): truncated value with size 32 to match size of target (13)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 VGA_controller.v(181) " "Verilog HDL assignment warning at VGA_controller.v(181): truncated value with size 32 to match size of target (13)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 181 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 VGA_controller.v(207) " "Verilog HDL assignment warning at VGA_controller.v(207): truncated value with size 32 to match size of target (13)" {  } { { "VGA_controller.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/VGA_controller.v" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1651562327404 "|vga_top|VGA_controller:vga_control"}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1651562328129 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 51 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|LEDR[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[1\] GND " "Pin \"HEX0\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[2\] GND " "Pin \"HEX0\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[3\] GND " "Pin \"HEX0\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[4\] GND " "Pin \"HEX0\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[5\] GND " "Pin \"HEX0\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[6\] GND " "Pin \"HEX0\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[7\] GND " "Pin \"HEX0\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 54 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX0[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[0\] GND " "Pin \"HEX1\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[1\] GND " "Pin \"HEX1\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[2\] GND " "Pin \"HEX1\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[3\] GND " "Pin \"HEX1\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[4\] GND " "Pin \"HEX1\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[5\] GND " "Pin \"HEX1\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[6\] GND " "Pin \"HEX1\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[7\] GND " "Pin \"HEX1\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 55 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[0\] GND " "Pin \"HEX2\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[3\] GND " "Pin \"HEX2\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[4\] GND " "Pin \"HEX2\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[5\] GND " "Pin \"HEX2\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] GND " "Pin \"HEX2\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[7\] GND " "Pin \"HEX2\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 56 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[0\] GND " "Pin \"HEX3\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[3\] GND " "Pin \"HEX3\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[4\] GND " "Pin \"HEX3\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[5\] GND " "Pin \"HEX3\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] GND " "Pin \"HEX3\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[7\] GND " "Pin \"HEX3\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 57 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX3[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[0\] GND " "Pin \"HEX4\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[2\] GND " "Pin \"HEX4\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[3\] GND " "Pin \"HEX4\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[4\] GND " "Pin \"HEX4\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[5\] GND " "Pin \"HEX4\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[6\] GND " "Pin \"HEX4\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[7\] GND " "Pin \"HEX4\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 58 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX4[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] GND " "Pin \"HEX5\[6\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[7\] GND " "Pin \"HEX5\[7\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 59 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|HEX5[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_SYNC_N GND " "Pin \"VGA_SYNC_N\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 67 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_SYNC_N"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[0\] GND " "Pin \"VGA_R\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 68 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_R[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[1\] GND " "Pin \"VGA_R\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 68 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_R[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Pin \"VGA_G\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 69 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_G[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Pin \"VGA_G\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 69 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_G[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Pin \"VGA_B\[0\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 70 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_B[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Pin \"VGA_B\[1\]\" is stuck at GND" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 70 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1651562328196 "|vga_top|VGA_B[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1651562328196 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1651562328311 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1651562328668 ""}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "vga 24 " "Ignored 24 assignments for entity \"vga\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity vga -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity vga -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity vga -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity vga -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity vga -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1651562328686 ""}  } {  } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1651562328686 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1651562328893 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1651562328893 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "11 " "Design contains 11 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 48 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 48 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|KEY[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "vga_top.v" "" { Text "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/vga_top.v" 45 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1651562328971 "|vga_top|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1651562328971 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "226 " "Implemented 226 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1651562328971 ""} { "Info" "ICUT_CUT_TM_OPINS" "87 " "Implemented 87 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1651562328971 ""} { "Info" "ICUT_CUT_TM_LCELLS" "124 " "Implemented 124 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1651562328971 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1651562328971 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 118 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 118 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4832 " "Peak virtual memory: 4832 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1651562329006 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 03 00:18:49 2022 " "Processing ended: Tue May 03 00:18:49 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1651562329006 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1651562329006 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:35 " "Total CPU time (on all processors): 00:00:35" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1651562329006 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1651562329006 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1651562330902 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1651562330902 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 03 00:18:50 2022 " "Processing started: Tue May 03 00:18:50 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1651562330902 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1651562330902 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga_top -c vga_top " "Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_top -c vga_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1651562330902 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1651562331074 ""}
{ "Info" "0" "" "Project  = vga_top" {  } {  } 0 0 "Project  = vga_top" 0 0 "Fitter" 0 0 1651562331075 ""}
{ "Info" "0" "" "Revision = vga_top" {  } {  } 0 0 "Revision = vga_top" 0 0 "Fitter" 0 0 1651562331075 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1651562331243 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1651562331244 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "vga_top 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"vga_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1651562331364 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1651562331460 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1651562331460 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1651562332059 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1651562332323 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "20 102 " "No exact pin location assignment(s) for 20 pins of 102 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1651562332649 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1651562349975 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 8 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 8 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1651562350277 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1651562350277 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1651562350277 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1651562350283 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1651562350283 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1651562350285 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1651562350286 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1651562350286 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1651562350287 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "vga_top.sdc " "Synopsys Design Constraints File file not found: 'vga_top.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1651562351393 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1651562351393 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1651562351409 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1651562351410 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1651562351410 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1651562351434 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1651562351435 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1651562351435 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_DIN " "Node \"ADC_DIN\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_DIN" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_DOUT " "Node \"ADC_DOUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_DOUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FAN_CTRL " "Node \"FAN_CTRL\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FAN_CTRL" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[34\] " "Node \"GPIO_0\[34\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[35\] " "Node \"GPIO_0\[35\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[34\] " "Node \"GPIO_1\[34\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[35\] " "Node \"GPIO_1\[35\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_TXD " "Node \"IRDA_TXD\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_TXD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET " "Node \"TD_RESET\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" {  } { { "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1651562351574 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1651562351574 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:19 " "Fitter preparation operations ending: elapsed time is 00:00:19" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1651562351582 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1651562360172 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1651562360757 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1651562362614 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1651562364761 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1651562367564 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1651562367564 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1651562369813 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X22_Y70 X32_Y81 " "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X22_Y70 to location X32_Y81" {  } { { "loc" "" { Generic "C:/Users/ziyua/Downloads/lab4.vga_top/vga_top/" { { 1 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X22_Y70 to location X32_Y81"} { { 12 { 0 ""} 22 70 11 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1651562377077 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1651562377077 ""}
