Project Title     Asynchronous Design and Applications





  • National Science Foundation (NSF)Making Asynchronous Design Practical – CAREER Award; 1997 – 2001(PI – Akella)
  • University of California, Faculty Research Award – Low Power Design Using Clock Gating,; 1997-1998
  • National Science Foundation (NSF)High-level Synthesis of Self-timed Circuits,– 1993-1996 (PI – Akella)



Short Description


Investigate design, analysis, testing and synthesis of asynchronous circuits and systems. Asynchronous Superscalar architecture and dynamic instructions scheduling




  1. Tony Werner
  2. Bret Stott
  3. David Johnson
  4. Nithya Raghavan


Selected Publications


      T. Werner, V. Akella.  COUNTERFLOW PIPELINE BASED DYNAMIC INSTRUCTION SCHEDULING.   Proceedings of Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 69-79.

      T. Werner and V. Akella. ASYNCHRONOUS PROCESSOR SURVEY.  IEEE Computer, Vol. 30, No. 11, pp. 67-76.

      K. Maheswar and V. Akella,.  PGA-STC: A PROGRAMMABLE GATE ARRAY FOR SELF-TIMED CIRCUITS.  International Journal of Electronics, Vol. 84, No. 3, pp. 255-267

      D. Johnson and V. Akella.  DESIGN AND ANALYSIS OF ASYNCHRONOUS ADDER.  IEE Proceedings for Computers and Digital Techniques, Vol. 145, No. 1, pp. 1-8.

      D. Johnson, V. Akella, and B. Stott. MICROPIPELINED SYNCHRONOUS DISCRETE COSINE TRANSFORM (DCT/IDCT) PROCESSOR. IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 731-740.

      V. Akella, N. H. Vaidya, and G. R. Redinbo. ASYNCHRONOUS  COMPARISON-BASED DECODERS FOR DELAY-INSENSITIVE CODES. IEEE Transaction on Computers, Vo. 47, No. 7, pp. 802-811.

      N. Raghavan, V. Akella, and S. Bakshi.  AUTOMATION INSERTION OF GATED CLOCKS AT REGISTER TRANSFER LEVEL.  Proceedings of the Twelfth International Conference on VLSI Design, IEEE Computer Society, pp. 48-54.

      T. Werner and V. Akella. AN ASYNCHRONOUS SUPERSCALAR ARCHITECTURE FOR EXPLOITING INSTRUCTION-LEVEL PARALLEISM. Proceedings of the International Symposium on Advanced Research on Asynchronous Circuits and Systems, ASYNC 2001, March 2001, pp. 140-151.