Project Title

 

High Performance and Low Power Programmable Architectures for Media Workloads

 

Collaborators Prof. Fred Chong, Prof. Diana Franklin, Prof. Bevan Baas

 

Funding

 

Analog Devices, MA – Integration of DSP with Reconfigurable Logic

(Unrestricted gift) (PI – Akella)

 

National Science Foundation (NSF) - ITR: SynchroScalar: A Tile-based Embedded Processor for Energy Efficient Multirate Embedded Systems (PI – Akella & Chong and Co-PI Prof. Baas)

 

 

Short Description

 

The goal of this project is to create  general-purpose programmable processor architectures that approach the efficiency of an application specific integrated circuits in term of energy consumption for next generation communication and signal processing workloads

 

 

Students

 

  1. John Oliver (ECE)
  2. Ravishankar Rao (CS)
  3. Paul Sultana (CS)
  4. Erik Czerknowski (ECE)
  5. Jeddiah Crendall (CS)

 

 

Publications

 

  1. John Oliver and Venkatesh Akella MAKING A DSP BETTER WITH A SMALL AMOUNT OF RECONFIGURABLE LOGIC, 13th International Conference on Field-Programmable Logic and Applications, Lecture Notes in Computer Science, 2778, Edited by P. Cheung, George Constantinides and Jose T. Sousa, pages 520-532, Springer Verlag 2003

 

  1. John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV*, Dean Copsey, Diana Keen, Venkatesh Akella, and Frederic T. Chong SYNCHROSCALAR: INITIAL LESSONS IN POWER-AWARE DESIGN OF TILE-BASED EMBEDDED PROCESSORS, Power-Aware Computing Systems (PACS) Workshop, December 2003, San Diego

 

  1. John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Keen, Venkatesh Akella, and Frederic T. Chong SYNCHROSCALAR: A MULTIPLE CLOCK DOMAIN POWER AWARE TILE-BASED EMBEDDED PROCESSOR, International Symposium on Computer Architecture, ISCA, June 2004

 

  1. John Oliver, Venkatesh Akella and Frederic T. Chong,  EFFICIENT ORCHESTRATION OF SUBWORD PARALLELISM IN SIMD ARCHITECTURES, Symposium on Parallelism in Algorithms and Architectures, SPAA, Barcelona, June 2004