EEC-270 – Computer Architecture

Winter Quarter 2005

Instructor	Venkatesh Akella (akella@ucdavis.edu)
Office Hours	5:10 -6:30 Wednesday
Classroom	1130 Bainer
Class Timing	Mon-Wed 3:40 PM – 5:00 PM

Overview of the Course

This is a graduate course in computer architecture. We will study modern computer architecture with special emphasis on the role of technology on processor design and techniques for exploiting instruction level parallelism and memory system design.

Prerequisites

An undergraduate course in computer architecture that includes quantitative performance analysis, pipelined processor design, caches and virtual memory is a required pre-requisite. People who do not have this pre-requisite should take EEC-170 before taking this class.

Books & References

Computer Architecture: A Quantitative Approach by Hennessy and Patterson Third Edition, 2003 (Absolutely Required).
Superscalar Microprocessor Design, Mark Johnson, Prentice-Hall 1992 is a good reference on superscalar processor design. (Optional).
Design of High-Performance Microprocessor Circuits, Edited by A. Chandrakasan, W. Bowhill, and F. Fox, IEEE Press, 2001. This is an excellent collection of tutorial papers on the implementation details of modern processors.
Proceedings of ISCA, MICRO, HPCA, ASPLOS (available from UC Davis online library)

Plan for the quarter

Needless to say, computer architecture is a rapidly evolving area with lots of activity in both the commercial and academic arenas; after all it is the basic building block for the information driven world. So, we will take a two-pronged approach to cover as much ground as possible. In the lectures we will cover the basic concepts – what drives innovation in computer architecture, instruction set design, exploiting instruction level parallelism, dealing with branches, reducing the processor-memory performance gap, I/O and storage networks. In parallel, you will be doing a term paper where you will explore a topic of your choice in more detail.

Tentative Course Schedule

Lecture	Topic	Reading Assignment
Week 1	Introduction	Chapter 1
Week 2	Instruction Set Design	Chapter 2
Week 3	Review of Pipelining	Appendix A
Week 4	Superscalar Processors Branch Prediction	Chapter 3
Week 5	VLIW and Software Pipelining	Chapter 4
Week 6	Thread level Parallelism	Chapter 6
Week 7	Memory System Design	Chapter 5
Week 8	Storage	Chapter 7
Week 9 and 10	Student Presentations

Examinations

Midterm Exam – February 16, 2005

Final Exam – Take Home

Grading Policy

Home works	25%
Midterm	25%
Presentation	10%
Term Paper	15%
Final	25%

Holidays

Monday - January 17, 2005 – Martin Luther King Holiday

Monday - February 21, 2005 – President’s Day

Term Paper Assignment

Homework 1 – Due Wednesday 1/19/2005

Solve the following problems from your textbook.

1.2, 1.7, 1.14, 2.5 and 2.12

Note that in problem 1.7 the clock cycle time is not given. Assume that the clock rate is the same for both processors and solve in terms of this unknown

Homework 2 – Due Wednesday 1/26/2005

Submit a project proposal. It should contain the following:

Title of the project

Summary of 3-5 key references that you read – strengths and weakness of each paper and key assumptions being made.

Problem Statement – In the form of a set of questions that you would like to answer.

Homework 3 – Due Wednesday 2/9/2005

Solve Problems 3.3, 3.6, 3.10, 3.18 and 3.28 from your text book

Homework 4 – Due Wednesday 3/9/2005

Solve the following problems from your textbook

Problem 4.6

Problem 4.9 (a) (b) (c) (e)

Problem 5.4 (a), (b), (c), (d), (e)

Additional Information for Problem 5.4

Note that the processor in this description is similar to the Sun UltraSPARC III described in Section 5.15 of the text. Looking at the description of that processor can be useful in understanding the issues involved in the solution of this problem. The problem statement says the L1 cache “imposes no penalty on hits.” The problem does not say anything about the execution time taken by a memory access instruction. That is, each memory access instruction must pass through the processor pipeline, incurring some execution latency. The solution will assume this latency is zero. Since the problem provides bus information, it is possible to include the effects of bus contention in the solution. The solution provided here assumes that the bus is able to support the required traffic.

Assume that cache miss penalties are cumulative. That is, there is no overlap between the miss penalty for the L1 cache and the L2 cache when a memory access must go to memory. Finally, we must consider how data is delivered when a request is satisfied using multiple bus transactions. It is possible to deliver the data with the critical (word or other portion) first but for simplicity you can assume delivery is in address order.