{"id":194,"date":"2015-05-13T08:53:31","date_gmt":"2015-05-13T16:53:31","guid":{"rendered":"http:\/\/www.ece.ucdavis.edu\/hsics\/?page_id=194"},"modified":"2015-05-13T08:53:31","modified_gmt":"2015-05-13T16:53:31","slug":"thz-interconnect","status":"publish","type":"page","link":"https:\/\/www.ece.ucdavis.edu\/hsics\/thz-interconnect\/","title":{"rendered":"THz Interconnect"},"content":{"rendered":"<p><strong>Background<\/strong><\/p>\n<p>Continuous scaling of semiconductor devices\u00a0allows more processor cores and integrated functionalities\u00a0into a single chip to support the growing\u00a0computation demands of scientific and\u00a0commercial workloads in both increasing\u00a0speed and volume. This trend mandates an ever increasing\u00a0inter-\/intra-chip communication bandwidth,\u00a0which has been a big challenge over\u00a0decades. This challenge has motivated active\u00a0research to improve interconnect capacities,\u00a0characterized by two key specs: bandwidth density,\u00a0defined as gigabits per second per square millimeter,\u00a0determining the aggregate throughput;\u00a0and energy efficiency, defined as Joules per bit,\u00a0indicating the overall power consumption. The\u00a0required off-chip I\/O bandwidth doubles about\u00a0every two years, significantly exceeding the\u00a0growth rate of the I\/O pin number due to packaging\/assembly limitations. The gap between\u00a0the interconnect requirement and the supporting capability\u00a0forms the \u201cinterconnect gap.\u201d With the projecting\u00a0trend,\u00a0the power consumption and\u00a0chip size to support interconnect only will be\u00a0intolerable\u00a0for most high performance computers and data centers in the near future\u00a0. In addition, cost, defined as dollars\u00a0per gigabit per second, also needs to scale down inversely proportional to the\u00a0interconnect bandwidth to be sustainable. To\u00a0support\u00a0the continuous demands for inter-\/intra- chip interconnect, the &#8220;interconnect gap&#8221; must be\u00a0filled.<\/p>\n<p><strong>Our Approach: THz Interconnect<\/strong><\/p>\n<p>To ultimately solve\u00a0the problem and close the gap, bandwidth\u00a0density, energy efficiency and cost should be all be significantly improved.\u00a0THz Interconnect (TI), utilizing the frequency\u00a0spectrum sandwiched between microwave and\u00a0optical frequencies,\u00a0holds high potential to\u00a0complement\u00a0Electrical Interconnect (EI) and Optical\u00a0Interconnect (OI) by leveraging the advantages\u00a0of both electronics and optics, as shown in Figure 1.\u00a0Continuous scaling of mainstream silicon\u00a0technologies enables terahertz electronics in silicon, which favors low cost and high reliability.\u00a0On the other hand, terahertz waveguides, similar to their optical counterparts, have\u00a0small dimensions and present low loss, which\u00a0alleviates the TI link budget to\u00a0allow low transmission output power and\u00a0improves the\u00a0energy efficiency.\u00a0In addition, TI\u00a0favors technology scaling because the increasing\u00a0frequency supports higher communication data\u00a0rates and reduces channel dimensions, thus\u00a0resulting in a larger bandwidth density.\u00a0These\u00a0unique features equip TI with\u00a0high energy efficiency, high bandwidth\u00a0density, low cost, and high resilience with the potential to\u00a0ultimately fill the<br \/>\ninterconnect gap.<\/p>\n<p><a href=\"http:\/\/www.ece.ucdavis.edu\/hsics\/wp-content\/uploads\/sites\/4\/2019\/12\/fig1-2.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-628\" src=\"http:\/\/www.ece.ucdavis.edu\/hsics\/wp-content\/uploads\/sites\/4\/2019\/12\/fig1-2.jpg\" alt=\"\" width=\"1086\" height=\"777\" srcset=\"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-content\/uploads\/sites\/4\/2019\/12\/fig1-2.jpg 1086w, https:\/\/www.ece.ucdavis.edu\/hsics\/wp-content\/uploads\/sites\/4\/2019\/12\/fig1-2-300x215.jpg 300w, https:\/\/www.ece.ucdavis.edu\/hsics\/wp-content\/uploads\/sites\/4\/2019\/12\/fig1-2-1024x733.jpg 1024w, https:\/\/www.ece.ucdavis.edu\/hsics\/wp-content\/uploads\/sites\/4\/2019\/12\/fig1-2-768x549.jpg 768w\" sizes=\"auto, (max-width: 1086px) 100vw, 1086px\" \/><\/a><\/p>\n<p><span style=\"color: #000000\"><b>Publications<\/b><\/span><\/p>\n<ol>\n<li>Y. Wang, B. Yu, Y. Ye, C.-N. Chen, Q. J. Gu, and Huei Wang, \u201cA G-Band On-Off-Keying Low Power Transmitter and Receiver for Interconnect Systems in 65-nm CMOS,\u201d Accept IEEE Transactions on Terahertz Science and Technology, Nov. 2019<\/li>\n<li>Q. J. Gu, Bo Yu, Xuan Ding, Yu Ye, Xiaoguang Liu, and Zhiwei Xu \u201cTHz interconnect: the last centimeter communication,\u201d SPIE, May 2019, <strong>Invited Paper<\/strong><\/li>\n<li>S. Ma, H. Yu, Q. J. Gu, and J. Ren, &#8220;A 5-10 Gbps 12.5 mW Source Synchronous I\/O Interface with 3D Flip Chip Package,&#8221; IEEE TCAS-I, vol. 66, Feb. 2019<\/li>\n<li>B. Yu, Y. Ye, X. Ding, C. Neher, X. Liu, Z. Xu, Q. J. Gu, \u201cSub-THz Interconnect for Planar Chip-to-Chip Communications,\u201d IEEE SiRF 2018, <strong>Invited Paper<\/strong><\/li>\n<li>B. Yu, Y. Ye, X. Ding, Y. Liu, Z. Xu, X. Liu, and Q. J. Gu, \u201cOrtho-Mode Sub-THz Interconnect Channel for Planar Chip-to-chip Communications\u201d, IEEE Transactions on Microwave Theory and Techniques, December 2017<\/li>\n<li>B. Yu, Y. Ye, X. Ding, Y. Liu, X. Liu, and Q. J. Gu, \u201cDielectric Waveguide Based Multi-Mode sub-THz Interconnect Channel for High Data-Rate High Bandwidth-Density Planar Chip-to-Chip Communication,\u201d IEEE International Microwave Symposium IMS2017, <strong>Best Student Paper Award, 3rd Place Winner<\/strong><\/li>\n<li>Y. Ye, B. Yu, X. Ding, X. Liu, and Q. J. Gu, \u201cHigh Energy-Efficiency High Bandwidth-Density Sub-THz Interconnect for the Last-Centimeter Chip-to-Chip Communications,\u201d IEEE International Microwave Symposium IMS2017<\/li>\n<li>Y. Ye, B. Yu, and Q. J. Gu, \u201cA 165 GHz Transmitter with 10.6% Peak DC-to-RF Efficiency and 0.68 pJ\/bit Energy Efficiency on 65 nm Bulk CMOS,\u201d IEEE Transactions on Microwave Theory and Techniques, pp. 4573-4584, vol.64, no. 12, Dec. 2016<\/li>\n<li>B. Yu, Y. Liu, Y. Ye, X. Liu, and Q. J. Gu, \u201cLow-loss and Broadband G-Band Dielectric Interconnect for Chip-to-Chip Communication,\u201d IEEE Microwave and Wireless Components Letter, June 2016<\/li>\n<li>B. Yu, Y. Liu, Y. Ye, Junyan Ren, X. Liu, and Q. J. Gu, \u201cHigh Efficiency Micromachined Sub-THz Channels for Low Cost Interconnect for Planar Integrated Circuits,\u201d IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 1, pp. 96-104, January 2016<\/li>\n<li>Q. J. Gu, \u201cTHz Interconnect, the Last Centimeter Communication,\u201d <em>IEEE Communication Magazine<\/em>, vol. 53, no. 4, pp.206-215, April 2015<\/li>\n<li>B. Yu, Y. Ye, X. Liu, Q. J. Gu, \u201cMicrostrip Line based Sub-THz Interconnect for High Energy-Efficiency Chip-to-Chip Communications,\u201d IEEE International Symposium on Radio-Frequency Integration Technology(RFIT), 2016<\/li>\n<li>S. Ma, J. Ren, N. Li, F. Ye, and Q. J. Gu, \u201cA Wideband and Low Power Dual-Band ASK Transceiver for Intra\/Inter-Chip Communication,\u201d 2015 IEEE International Microwave Symposium<\/li>\n<li>Q. J. Gu, \u201cIntegrated Circuits and Systems for THz Interconnect,\u201d 2015 <em>IEEE Wireless and Microwave Conference<\/em>, <strong>Invited Paper<\/strong><\/li>\n<li>B. Yu, Y. Liu, X. Hu, X. Ren, X. Liu, and Q. J. Gu, \u201cMicromachined Sub-THz Interconnect Channels for Planar Silicon Processes,\u201d 2014 <em>IEEE International Microwave Symposium<\/em><\/li>\n<li>B. Yu, Y. Liu, X. Hu, X. Ren, X. Liu, and Q. J. Gu, \u201cMicromachined Silicon Channels for THz Interconnect,\u201d 2014 IEEE Wireless and Microwave Conference, <strong>Best Conference Paper Award<\/strong><\/li>\n<li>Q. J. Gu, Z. Xu, and M.-C. F. Chang, \u201cMillimeter Wave and Sub-millimeter Wave Circuits for Integrated System-On-a-Chip,\u201d 2011 <em>IEEE International Symposium on Radio-Frequency Integration Technology(RFIT), <\/em><strong>Best Paper Award<\/strong><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"<p><strong>Background<\/strong><\/p>\n<p>Continuous scaling of semiconductor devices\u00a0allows more processor cores and integrated functionalities\u00a0into a single chip to support the growing\u00a0computation demands of scientific and\u00a0commercial workloads in both increasing\u00a0speed and volume. This trend mandates an ever increasing\u00a0inter-\/intra-chip communication bandwidth,\u00a0which has been a big challenge over\u00a0decades. This challenge has motivated active\u00a0research to improve  \u2026 <a href=\"https:\/\/www.ece.ucdavis.edu\/hsics\/thz-interconnect\/\"> Continue reading <span class=\"meta-nav\">&rarr; <\/span><\/a><\/p>\n","protected":false},"author":13,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-194","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/pages\/194","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/users\/13"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/comments?post=194"}],"version-history":[{"count":0,"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/pages\/194\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.ece.ucdavis.edu\/hsics\/wp-json\/wp\/v2\/media?parent=194"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}