4 units – Winter Quarter
Lecture: 3 hours
Prerequisite: EEC 150B, EEC 170, EEC 180B, or consent of instructor
Grading: homework/projects (65%), quizzes(15%), final exam (20%).
Digital signal processors, building blocks, and algorithms. Design and implementation of processor algorithms, architectures, control, functional units, and circuit topologies for increased performance and reduced circuit size and power dissipation.
Expanded Course Description:
The primary goal of this course is to develop the necessary skills for students to design simple digital signal processors with an emphasis on the efficient simultaneous design of algorithms, processor architectures, and hardware design.
- Digital signal processing overview
- DSP workloads
- Example applications
- Programmable processors
- Processor building blocks
- Verilog hardware description language
- Binary number representations
- Carry-propagate adders
- Carry-save adders
- Fixed-input multipliers
- Complex arithmetic hardware
- DSP algorithms and systems
- FIR filtering
- Processor control and data-path integration
- Multi-rate signal processing
- Example systems: FFT, Viterbi, DSSS, CDMA, etc.
- Design optimization
- Verilog synthesis to a gate netlist
- Delay estimation and reduction
- Area estimation and reduction
- Power estimation and reduction
- Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation.
- Rudra Pratap, Getting Started with Matlab.
- Behrooz Parhami, Computer Arithmetic, Algorithms and Hardware Design.
Introductory review material briefly overlaps prerequisite courses EEC150B, 170, and 180B. In addition, small amounts of material overlap may occur with the following courses: EEC 201 – filter design (minimal); EEC 215 – communication processing function as an example (minimal); EEC 218 – VLSI design methodologies overview (minimal); EEC 278 – some functional unit basics (focus on hardware, not algorithms); EEC 280 – possible pipelining overlap, but with DSP processors; ECS 231 – FFT (emphasis in this class on hardware).
Last revised:October 2018