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EEC146A – Integrated Circuits Fabrication

3 units – Fall Quarter

Lecture: 2 hours

Laboratory: 3 hours

Prerequisites: EEC 140A

Grading: Letter.

Catalog Description:

Basic fabrication processes for metal oxide semiconductor (MOS) integrated circuits. Laboratory assignments covering oxidation, photolithography, impurity diffusion, metallization, wet chemical etching, and characterization work together in producing metal-gate PMOS test chips which will undergo parametric and functional testing.

Expanded Course Description:

  1. Clean Room Processing
    1. Safety with Process Chemicals and Processing Equipment
    2. Contamination Control
    3. Chemical Cleaning and Polishing
  2. Basic Integrated Circuits Processes
    1. Wet and Dry Oxidation for Fields and Gates
    2. Spincoating Resists and Softbake
    3. Contact Photoexposure and Image Development
    4. Patterning by Wet Chemical Etching and Liftoff
    5. Impurity Predeposition Using Solid Sources
    6. Junction Formation and Dopant Diffusion
    7. Metal Deposition by Evaporation
    8. Annealing and Interface Charge Passivation
  3. Basic Materials Characterization Techniques
    1. Thermal Probe Measurements
    2. Four-Point Resistivity Analysis
    3. Ellipsometry and Color Analysis of Silicon Dioxide Films
    4. Determination of Etch Rates
    5. Groove and Stain Junction Measurements
  4. Basic Parametric and Functional Testing
    1. Device Probing
    2. I-V Measurements of MOS Devices
    3. Threshold Measurements
    4. Metal to Semiconductor Interfaces
    5. Junction Breakdown
    6. Ring Oscillators and Performance Benchmarks

Laboratory Projects:

Ten weekly three hour laboratory projects. The students calculate fabrication process variables and fully fabricate a working MOS test chip. The fabrication procedures used in any given week’s lab correspond to the technology being presented in the lectures that week, thereby providing immediate hands-on experience. Process monitoring and in-progress process variable adjustment and modification are key issues in the lab assignments. Functional and parametric testing of working devices and circuits is performed in the last lab.


  1. R. Jaeger, Introduction to Microelectronic Fabrication, Vol. V, Prentice Hall.
  2. S. Ghandi, VLSI Fabrication Principles, Wiley.

Engineering Design Statement:

Since no single process flow is “correct” for obtaining the final IC being processed, students are required to learn to make tradeoffs to optimize the ultimate circuit performance. Most problems in the class are open-ended with different approaches being valid according to initial conditions of the IC and the technology chosen. Students learn to design a process to optimize performance and yield, and minimize complexity and parasitic effects. Students are required to compare theory with experimental results and to justify the differences. They are furthermore required to predict where digression from theory is likely to occur and account for this in setting fabrication operating parameters.

Relationship to Outcomes:

Students who have successfully completed this course should have achieved:

Course Outcomes ABET Outcomes
An ability to apply knowledge of mathematics, science, and engineering A
An ability to design and conduct experiments, as well as to analyze and interpret data B
An ability to communicate effectively G
An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. K


Professional Component:

Engineering Depth, Laboratory

Engineering Science: 1 credit
Engineering Design: 2 credits