MediaDSP3201

MediaDSP3201 implemented reduced instruction set computer (RISC) and single instruction multiple data (SIMD) instruction set architecture with various addressing mode in a unified RISC/DSP pipeline stage architecture , which was developed by Zhejiang University in 2003. MediaDSP3201 targets diverse embedded application systems, which require both powerful processing/control capability and low-cost budget, e.g. set-top-boxes, video conferencing, DTV, etc. The processor can achieve 320MIPS 32bit x 32bit multiply-accumulate (MAC) and 1280MIPS 16bit x 16bit MAC operations. The processor was taped out at TSMC(0.18um M6 CMOS technology) and dissipates 600mW at 1.8v, 300MHz. The following picture shows the testing platform for this processor. A small test board carrying the chip can be directly inserted into the mother PCB board. PCs can be used to communicate with the test PCB board with the USB port.

This page last modifed at 03/28/2007 .