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WHY UC DAVIS ENGINEERING (FROM MY PERSONAL EXPERIENCE):
- Personal attention
to students
- Great learning environment
- Learn practical problem solving skills (not just reciting the textbooks)
- Really think outside the box
CAN'T MISS GRADUATE EE COURSES:
EEC 210 MOS Analog Circuit Design
EEC 270 Computer Architecture
EEC 282 Dig Systems Modeling & Design
EEC 216 Low Power Dig IC Design
EEC 281 VLSI Digital Sig Processing
EEC 284 Embedded Comp System
MY
RESEARCH:
Dynamic Voltage and Frequency Scaling on Multiple Voltage Domain Architectures
MY PUBLICATIONS:
Wayne Cheng, Bevan Baas,
"Dynamic Voltage and Frequency Scaling Circuits with Two Supply Voltages,"
IEEE International Symposium on Circuits and Systems (ISCAS), May
2008, to appear.
MY
RESUME (email me for a copy):
OBJECTIVE
A position as a
VLSI or ASIC design engineer
EXPERIENCE / RESEARCH
Uniquify Inc.
2007-Present
Integrated Perl scripting into back-end physical design flow
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Verified LIB and LEF technology library files
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Automatically generated timing constraints (SDC) and floorplan from RTL
Iterated
through back-end physical design flow with Magma EDA tools
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Wrote TCL scripts to automate logic synthesis,
cell placement, clock tree synthesis (CTS), cell routing, timing analysis,
and power analysis
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Wrote Shell scripts to maximize computing
resources, constantly iterating through flows with multiple physical design
scripts
Performed sign off procedure with Synopsys Primetime static
timing analysis (STA) tool
VCL (VLSI Computation Laboratory) Group
University
of California, Davis
2006-2007
Participated in the design of a 65nm multi-core chip, with
167 fine-grain programmable processors connected by a reconfigurable
asynchronous mesh network (taped out on June 2007; functional chip
received on September 2007)
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Able to reach a maximum operating frequency of
1.1 GHz (highest clock rate for a chip designed in a university)
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Automatic dynamic voltage and frequency scaling
on each processor made possible by local oscillators and supply switching
circuits
Full custom power gates designed for fine-grain dynamic
voltage scaling
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Gate layout is designed from scratch with Cadence
Virtuoso in ICFB
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Examined optimal placement of transistors, power
stripes, and contacts within the design rule guidelines, minimizing area,
noise, and maximizing performance
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Created and integrated cell libraries into
various EDA tools
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Simulated extracted netlist over multiple
process, voltage, and temperature (PVT) operating conditions with SPICE
Asynchronous circuit designed for dynamic voltage supply
switching
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State machine made possible using standard cell
gate delays; cells are sized for adequate gate drive and correct timing
Dynamic voltage and frequency scaling logic control block
constructed in Verilog RTL
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Synchronized signals across unrelated clock
domains
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Performed logic synthesis on RTL with Synopsys
Design Compiler, using Synopsys design constraint scripts (SDC)
optimized for area and power minimization
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Verified functionality of RTL and gate level
netlist with Mentor Modelsim, Cadence NCVerilog and SimVision
Iterated through physical design flow with Cadence SOC
Encounter
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Constructed layout of processor wrapper using
custom and standard cell libraries
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Wrote TCL scripts, automating floorplan creation,
cell placement, clock tree synthesis, cell routing, and timing and power
analysis
Sign-off procedure performed to verify logic and timing
robustness
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Set up Calibre design rule check (DRC) and layout
versus schematic (LVS) test flows to validate design
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Wrote and ran targeted tests in AsAP Assembly
Language
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Identified and debugged timing issues on
back-annotated design, importing standard delay format (SDF) and RC
parasitics (SPEF)
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Set up Synopsys Nanosim testing environments for
final confirmation
Graduate Class Projects
University
of California, Davis
2005-2007
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Code Division Multiple Access (CDMA) Transmitter
and Receiver in Verilog and Matlab
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32-point Fast Fourier Transform (FFT) engine in
Verilog and Matlab
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Delayed Least Mean Squares (DLMS) filter;
exploration of hardware/software co-design with C and Verilog, simulated on
an Altera Excalibur Platform with SimpleScalar
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General-purpose programming on graphics
processing units (GPGPU) of dynamic programming algorithms with C and OpenGL
Senior Design Projects
University
of California, San Diego
2005
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Firmware programming on Microchip
microcontroller, with ADC interface and motor control for SPAWAR’s miniature
3D sensor
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Programming of JavaScript based API on a DPAC
board for WiFi controlled toy car
EDUCATION
Master of Science in Electrical Engineering
University of California, Davis
Graduate GPA: 3.63; Overall GPA: 3.57
Expected graduation date: February 2008
Bachelor of Science in Electrical Engineering
University of California, San Diego
Overall GPA: 3.21
PUBLICATIONS
Wayne H. Cheng, Bevan M. Baas,
““Run-time Dynamic Voltage and Frequency Scaling,” International
Symposium on Circuits and Systems (ISCAS) 2008, Accepted.
Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu,
Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul
Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas, “A
167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply
Voltage and Dynamic Clock Frequency Scaling,” VLSI Symposium 2008,
In Review.
Wayne H. Cheng, Bevan M. Baas, ““Joint
Dynamic Supply Voltage and Clock Frequency Scaling in Fine-Grain GALS
Multiprocessors,” IEEE Transactions on Very Large Scale Integration
Systems (TVLSI), in preparation.
SKILLS SUMMARY
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PERL,
TCL, SH, CSH, C, C++, Java, LISP, Prolog, HTML, PHP, SQL
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RTL, Verilog, LEF, LIB, EDA, SDC, STA, SDF, SPEF,
SPICE
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Fluency in mandarin Chinese (speaking)
TAPEOUT OF ASAP 2.0 ON JUNE 24TH, 2007:
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