ECE 278: Selected Papers

 

 

  1. Kilburn T., D. B. G. Edwards, and D. Aspinall, “Parallel Addition in Digital Computers: A New Fast “Carry” Circuit”, Proceedings of IEE, Vol 106, pt B, p.464, September 1959.

 

  1. V. G. Oklobdzija and E. R. Barnes, "Some Optimal Schemes For ALU Implementation In VLSI Technology," Proceedings of the 7th Symposium on Computer Arithmetic ARITH-7, pp. 2-8. Reprinted in Computer Arithmetic, E. E. Swartzlander, (editor), Vol. II, pp. 137-142, 1985.

 

  1. V. G. Oklobdzija and E. R. Barnes, "On Implementing Addition In VLSI Technology," IEEE Journal of Parallel and Distributed Computing, No. 5, pp. 716-728, 1988.

 

  1. V. G. Oklobdzija, "Simple And Efficient CMOS Circuit For Fast VLSI Adder Realization", Proceedings of the International Symposium on Circuits and Systems, pp. 1-4, 1988.

 

  1. A. Weinberger and J. L. Smith, “A Logic for High-Speed Addition”, National Bureau of Standards, Circ. 591, p.3-12, 1958.

 

  1. A. Naini, D. Bearden and W. Anderson, “A 4.5nS 96b CMOS Adder Design”, Proceedings of the IEEE Custom Integrated Circuits Conference, May 3-6, 1992, p 25.5.1 - 25.5.4.

 

  1. B. D. Lee and V. G. Oklobdzija, "Improved CLA Scheme With Optimized Delay," Journal of VLSI Signal Processing, Vol. 3, No. 4, pp. 265-274, 1991.

 

  1. H. Ling, “High-Speed Binary Adder”, IBM J. Res. Dev., vol.25, p.156-66, 1981.

 

  1. S. Nafziger, “A Sub-Nanosecond 0.5um 64b Adder Design”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference,  San Francisco, 8-10 Feb. 1996, p.362 –363.

 

  1. R. P. Brent and H. T. Kong, “A Regular Layout for Parallel Adders”, IEEE Transactions on Computers, Vol. C-31, No.3, March 1982, p.260-264.

 

  1. J. Sklansky, “Conditional-Sum Addition Logic”, IRE Transactions on Electronic Computers, EC-9, p.226-231, 1960.

 

  1. O. J. Bedrij, “Carry-Select Adder”, IRE Transactions on Electronic Computers, June 1962, p.340-34

 

  1. A. Farooqui, V. G. Oklobdzija, F. Chehrazi, "Multiplexer Based Adder for Media Signal Processing", 1999 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, June 8-10, 1999.