-- mult4x4.vhd -- Mealy machine based on design in Section 4.3 of Roth VHDL text -- 5/6/99 LH Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity mult4x4 is port (clk, reset, Start : in std_logic; Mplier, Mcand : in std_logic_vector(3 downto 0); Product : out std_logic_vector(7 downto 0)); end mult4x4; architecture behave of mult4x4 is signal State, NextState : integer range 0 to 9; signal ACC : std_logic_vector(8 downto 0); signal Ld, Ad, Sh, St : std_logic; signal M : std_logic; begin Product <= not ACC(7 downto 0); -- display lowest 8 bits (active low) M <= ACC(0); -- alias not supported for synthesis LOGIC : process(State, St, M) begin NextState <= 0; -- defaults to prevent latches Ld <= '0'; Ad <= '0'; Sh <= '0'; case State is when 0 => if St='0' then -- St active low Ld <= '1'; NextState <= 1; else -- could just "end if" here NextState <= 0; -- this is default value anyway... end if; when 1 | 3 | 5 | 7 => if M='1' then Ad <= '1'; NextState <= State+1; else Sh <= '1'; NextState <= State+2; end if; when 2 | 4 | 6 | 8 => Sh <= '1'; NextState <= State+1; when 9 => NextState <= 0; end case; end process; Regs: process(clk, reset) begin if reset='0' then State <= 0; -- State register St <= '0'; -- St is synchronized to clk elsif clk'event and clk='1' then State <= NextState; St <= Start; -- St is synchronized Start end if; end process; Shift_reg : process(clk, reset, Ld, Ad, Sh) begin if reset='0' then -- Asynchronous reset ACC <= "000000000"; elsif clk'event and clk='1' then -- Synchronous operations if Ad='1' then ACC(8 downto 4) <= ('0' & ACC(7 downto 4)) + ('0' & Mcand); elsif Sh='1' then ACC <= '0' & ACC(8 downto 1); elsif Ld='1' then ACC <= "00000" & Mplier; end if; end if; end process; end behave; -- architecture configuration mult4x4_cfg of mult4x4 is for behave end for; end mult4x4_cfg;