EEC180B                                                                      DIGITAL SYSTEMS II                                                                 Spring 1999

Reading Assignments

Instructor: Prof. Vojin G. Oklobdzija
Course Overview and Tentative Schedule (reading assignments)


Schedule of the Lectures
Schedule of the Labs
Week 1: (April 5-11) 

Reading: Chpt. 6, 8, 9, 10, 11, A1-4

Course overview, Review of the laboratory assignment and project

No Labs
Week 2: (April 12-18)

Reading: Chpt. 6, 8, 9, 10, 11, 26, A1-4

Review of the Logic Design (180A): 

Karnaugh Maps, Multi-level Gate Networks, Flip-Flops, Hazards

Lab 1:

Introduction to PowerView CAD

Week 3: (April 19-25) 

Reading: Chpt . 10, 11, 12, 13, 14, 15, 16

Review of the Logic Design (180A): 

Counters and Sequential Networks, FSM design, FSM diagram and representations.

Examples.

Lab 2:
 

Introduction to Xilinx CAD
 

Week 4: (April 26-May 2) 

Reading: Chpt. 17, 20

Iterative Networks, Networks for Addition/Subtraction.

Lab 3:
 

Register File Design
 

Week 5: (May 3-9)

Reading: Chpt. 4*, 20

Computer Arithmetic: ALU design, Multiplication.

Lab 4:

ALU Design

 

Week 6: (May 10-16) 

Reading: Chpt. 3*, 18

Basic Computer Organization, Computer Instructions- interface with the control logic, MSI Integrated Circuits.

Lab 5:
 

Logic Analyzer Tutorial
 

Week 7: (May 17-23) 

Reading: Chpt. 19, 5*

Sequential Network Design - FSM Using PLAs and PLDs, Microprogramming:

Lab 6:
 

Memory Interface Design

 

Week 8: (May 24-30)

Reading: Chpt. 5*, 22, 23, C

Design of ControlUnit, Various design styles. Mapping Control to Hardware

Lab 7:

Memory Interface Design (continued)

Week 9: (May 31 -June 6)

Reading: Chpt. 24, 25, 

Derivation and Reduction of Primitive Flow-Tables, State Assignment and Realization of Flow-Tables.

Lab 8:
 

MISP Processor Design

Week 10: (June 7-9) 

Reading: Chpt. 6*

Enhancing performance with pipelining.

Lab 9:

MISP Processor Design (continued)