My research interests are in high performance and energy efficient
signal processing and error correction algorithms and circuits.
I am currently working on algorithms and architectures for very high throughput and high energy efficiency Low Density Parity Check (LDPC) decoders.
I was a key member who designed and tapedout the second generation many-core chip
(AsAP 2.0) with 167 processors in 65 nm.
AsAP (Asynchronous array of
simple processors) is a many-core chip targeting computationally-demanding multi-task DSP system applications.
Dean N. Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu,
Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen,
Christine Watnik, Anh T. Tran, Zhibin Xiao, Eric W. Work,
Jeremy W. Webb, Paul V. Mejia, Bevan M. Baas,
"A 167-Processor Computational
Platform in 65 nm CMOS," IEEE Journal of Solid-State Circuits (JSSC),
vol. 44, no. 4, pp. 1130-1144, April 2009. Invited.
Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai,
Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas,
"AsAP: An
Asynchronous Array of Simple Processors," IEEE Journal of Solid-State Circuits (JSSC),
vol. 43, no. 3, pp. 695-705, March 2008.
Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson,
Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong,
Jason Cheung,
"AsAP:
A Fine-grain Multi-core Platform for DSP Applications," IEEE Micro, Volume 27, Number 2, March/April 2007. Invited.
Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai,
Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas,
"An Asynchronous
Array of Simple Processors for DSP Applications,"
In Proceedings of the IEEE International Solid-State Circuits
Conference (ISSCC '06), February 2006, pp. 428-429, 663.