Tinoosh Mohsenin

                       PhD candidate

                       VLSI Computation Lab

                       Department of Electrical and Computer Engineering.

                       University of California, Davis

                       Office: Room 2211, Kemper Hall

                       Email: tmohsenin at ucdavis.edu

                       Phone: 530-752-5074

 

 

 

 

I am currently a PhD student in Electrical and Computer Engineering Department. Professor Bevan Baas is my PhD adviser at University of California, Davis.  I received my Bachlors degree in Electrical Engineering from  Sharif University of Technology, Tehran, Iran, and my Masters in Electrical and Computer Engineering  from Rice University, Houston, Texas.
 

My research interests are in high performance and energy efficient signal processing and error correction algorithms and circuits. I am currently working on algorithms and architectures for very high throughput and high energy efficiency Low Density Parity Check (LDPC) decoders. I recently participated in the design and fabrication of my group's second generation many-core chip (AsAP 2.0) with 167 processors in 65 nm. AsAP (Asynchronous array of synchronous processors) is a multi-processor chip which was designed and fabricated in a 0.18 μm CMOS by my colleagues in VCL lab in 2005.

 

Resume

 

Personal

 

I enjoy skiing, playing tennis, kayaking, painting, camping, traveling and hanging out with friends.

 

Misc

 

The Error Correcting Code page

Matlab files for LDPC decoder

VI cheat sheet

R. M. Gray, Books

Conferences for Architectures and Signal Processing


Recent Presentations

 

  • Feb 02 2008 , "An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder", ISSCC Student Forum
  • Feb 26 2008 , Plato Networks.
  • March 13 2008 , Invited speaker by JPL at Caltech

    Publications

     

  • Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik,
    Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
    "A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing,"
    In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, August 2008, to appear.

  • Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik,
    Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
    "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling,"
    Symposium on VLSI Circuits, June 2008, to appear .

  • Tinoosh Mohsenin, Bevan M. Baas, " High-Throughput LDPC Decoders Using A Multiple Split-Row Method", In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'07), April 2007.

  • Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Bevan Baas,
    "Architecture and Evaluation of an Asynchronous Array of Simple Processors,"
    Journal of VLSI Signal Processing Systems, in press.

  • Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas,
    "AsAP: An Asynchronous Array of Simple Processors,"
    IEEE Journal of Solid-State Circuits (JSSC), in press.

  • Tinoosh Mohsenin, Bevan M. Baas, " Split-row: A Reduced Complexity, High Throughput LDPC Decoder Architecture ", In Proceedings of the IEEE International Conference of Computer Design (ICCD '06), October 2006.

  • Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas,
    "A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains,"
    IEEE Transactions of Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

  • Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung,
    "AsAP: A Fine-grain Multi-core Platform for DSP Applications," IEEE Micro, Volume 27, Number 2, March/April 2007.
    Invited.

  • Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin, "Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors," In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2006), August 2006.

  • Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas, " An Asynchronous Array of Simple Processors for DSP Applications," In Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06), February 2006, pp. 428-429.

  • Junqiang Hu; Zhong Pan; Zuqing Zhu; Haijun Yang; Mohsenin, T.; Akella, V.; Ben Yoo, S.J, "First Experimental Demonstration of IP-Client-to-IP-Client Video Streaming Application Over an All-Optical Label-Switching Network with Edge Routers", Optical Fiber Communication Conference (OFC'05),Volume 5, March 2005.

  • T.Mohsenin, "Design and Evaluation of FPGA-Based Gigabit-Ethernet/PCI Network Interface Card", Masters Thesis, Rice University, 2003.

  • P.Murphy, J.P.Frantz, E.Welsh, R.Hardy, T.Mohsenin and J.Cavallaro, "VALID: Custom ASIC Verification and FPGA Education Platform", Microelectronic Systems Education Conference, (MSE'03),  June 2003, pp. 64 - 65.

    This page last modified on May, 2008