Tinoosh Mohsenin

                       PhD candidate

                       VLSI Computation Lab

                       Department of Electrical and Computer Engineering.

                       University of California, Davis

                       Office: Room 2211, Kemper Hall

                       Email: tmohsenin at ucdavis.edu

                       Phone: 530-752-5074

I am currently a PhD student in Electrical and Computer Engineering Department at UC Davis and my PhD adviser is Professor Bevan Baas. I received my Bachelors degree in Electrical Engineering from  Sharif University of Technology, Tehran, Iran, and my Masters degree in Electrical and Computer Engineering from Rice University. My research interests are in high performance and energy efficient signal processing and error correction algorithms and circuits.

• High Throughput and Energy Efficient Low Density Parity Check (LDPC) Decoders
  I designed Split-Row, Multi-Split and Split-Row Threshold algorithms which reduce the complexity of the processor's logic and local and global interconnections. Our chip implementation results show significant improvements in logic utilization, silicon area, throughput and energy efficiency. For more details see this paper.

• Many-core Processor Architecture Design
  I was a key member in design and tapeout of the second generation many-core chip (AsAP 2.0) with 167 processors in 65 nm. AsAP (Asynchronous array of simple processors) is a many-core chip targeting computationally-demanding multi-task DSP system applications. For more details see our JSSC paper.

• December 11, 2009, University of Washington, Seattle, WA.
• November 2, 2009, Asilomar Conference, Monterey, CA.
• September 17, 2009, Rice University, Houston, TX.
• September 16, 2009, Texas Instruments, Dallas, TX.
• September 15, 2009, TECHCON 2009, Austin, TX.
• August 20, 2009, IEEE Santa Clara Valley (SCV) Solid State Circuits Society .
• July 23, 2009, Aquantia, Milpitas, CA.
• May 22, 2009, National Chiao Tung University (NCTU), Hsinchu, Taiwan.
• May 28, 2009, National Taiwan University (NTU), Taipei, Taiwan.
• March 13, 2008, Invited speaker by NASA JPL at Caltech, Pasadena, CA.
• February 26, 2008, Plato Networks, Santa Clara, CA.
• February 02, 2008, "An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder", IEEE International Solid-State Circuits Conference (ISSCC) 2008 Student Forum.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  " A Low Complexity Message Passing Algorithm for Reduced Routing Congestion in LDPC Decoders,"
  Accepted in IEEE Transactions of Circuits and Systems I, Invited.

• Tinoosh Mohsenin and Bevan Baas,
  " A Split-Decoding Message Passing Algorithm for Low Density Parity Check Codes,"
  Accepted in Journal of VLSI Signal Processing.

• Tinoosh Mohsenin and Bevan Baas,
  " Trends and Challenges in LDPC Hardware Decoders,"
  Asilomar Conference on Signals, Systems and Computers (ACSSC), November 2009.
  Invited.

• Tinoosh Mohsenin and Bevan Baas,
  " High Throughput and Energy Efficient LDPC Decoders using Multi-Split-Row Threshold Method,"
  TECHCON 2009, September 2009.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "An Improved Split-Row Thresholding Decoding Algorithm for LDPC Codes,"
  IEEE International Conference on Communications (ICC'09), June 2009.

• Tinoosh Mohsenin, Dean Truong and Bevan Baas,
  "Multi-Split-Row Threshold Decoding Implementations for LDPC Codes,"
  IEEE International Symposium on Circuits and Systems (ISCAS'09), May 2009.

• Dean N. Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen,
  Christine Watnik, Anh T. Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul V. Mejia, Bevan M. Baas,
  "A 167-Processor Computational Platform in 65 nm CMOS,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 4, pp. 1130-1144, April 2009.
  Invited.

• Tinoosh Mohsenin, Pascal Urard and Bevan Baas,
  "A Thresholding Algorithm for Improved Split-Row Decoding of LDPC Codes,"
  Asilomar Conference on Signals, Systems and Computers (ACSSC), October 2008.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik,
  Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2008), August 2008.

• Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik,
  Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas,
  "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling,"
  Symposium on VLSI Circuits, June 2008, C3.1.

• Tinoosh Mohsenin and Bevan Baas,
  "An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder,"
  IEEE International Solid-State Circuits Conference (ISSCC) 2008 Student Forum, February 2008.

• Tinoosh Mohsenin and Bevan Baas,
  " High-Throughput LDPC Decoders Using A Multiple Split-Row Method,"
  In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'07), April 2007.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Bevan Baas,
  "Architecture and Evaluation of an Asynchronous Array of Simple Processors,"
  Journal of VLSI Signal Processing Systems, March 2008.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas,
  "AsAP: An Asynchronous Array of Simple Processors,"
  IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, March 2008.

• Tinoosh Mohsenin, Bevan M. Baas,
  " Split-row: A Reduced Complexity, High Throughput LDPC Decoder Architecture",
  In Proceedings of the IEEE International Conference of Computer Design (ICCD '06), October 2006.

• Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas,
  "A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains,"
  IEEE Transactions of Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung,
  "AsAP: A Fine-grain Multi-core Platform for DSP Applications,"
  IEEE Micro, Volume 27, Number 2, March/April 2007.
  Invited.

• Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin,
  "Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors,"
  In Proceedings of the IEEE HotChips Symposium on High-Performance Chips, (HotChips 2006), August 2006.

• Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas,
  "An Asynchronous Array of Simple Processors for DSP Applications,"
  In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '06), February 2006, pp. 428-429, 663.

• Junqiang Hu; Zhong Pan; Zuqing Zhu; Haijun Yang; Mohsenin, T.; Akella, V.; Ben Yoo, S.J, "First Experimental Demonstration of IP-Client-to-IP-Client Video Streaming Application Over an All-Optical Label-Switching Network with Edge Routers", Optical Fiber Communication Conference (OFC'05),Volume 5, March 2005.

• Tinoosh Mohsenin, "Design and Evaluation of FPGA-Based Gigabit-Ethernet/PCI Network Interface Card", Masters Thesis, Rice University, 2003.

• P.Murphy, J.P.Frantz, E.Welsh, R.Hardy, T.Mohsenin and J.Cavallaro, "VALID: Custom ASIC Verification and FPGA Education Platform", Microelectronic Systems Education Conference, (MSE'03),  June 2003, pp. 64 - 65.

• T. Mohsenin, P. Urard and B. Baas,
  "Improved Split-Row Decoding of LDPC Codes", US patent pending, filed 2009.
  
• Tinoosh Mohsenin, and Bevan Baas,
  "10GBASE-T LDPC Encoder/Decoder Research Chip,"
  Proposal submitted to STMicroelectronics, September 2008.
• Tinoosh Mohsenin, and Bevan Baas,
  "Ultra Low Power 10GBASE-T LDPC Decoder Research Chip,"
  Proposal submitted to STMicroelectronics, August 2009.

Misc Items

The Error Correcting Code page

Matlab files for LDPC decoder

VI cheat sheet

R. M. Gray, Books

Conferences for Architectures and Signal Processing