| 2064 Kemper Hall | (530) 752-0583 |
| Davis, CA 95616-5294 | Fax: (530) 752-8428 |
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The VLSI Computation Laboratory, led by Prof. Bevan Baas, used Cadence tools to design and perform pre-silicon verification on a globally-asynchronous locally-synchronous (GALS) array of simple processors which enables energy efficient implementations of complex digital signal processing applications. More details on the AsAP-1 chip can be found here. |
Professor Rajeevan Amirtharajah |
Professor Paul Hurst |
Professor Anh-Vu H. Pham |
Professor Bevan Baas |
Professor Stephen H. Lewis |
Professor Richard Spencer |
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Professor K. Wayne Current |
Professor John D. Owens |
| EEC 216 Low Power Digital IC Design | EEC 281 VLSI Digital Signal Processing | |
| EEC 210 MOS Analog Design | EEC 289T Signal Integrity | |
| EEC 222 RFIC Design |
| Micropower Circuits and Systems Group | Microwave Microsystems Research Laboratory | Solid-State Circuits Research Laboratory |
| VLSI Computation Laboratory |