* EEC 216 W09 Design Project 1
* File: dp1.sp
* Author:  anystudent@ucdavis
* Date: 01/28/09
**
** 
** Design Project 1: Logic Gate Design
** Last edited: Jan 28 10:42 2009 (ramirtha)
**----------------------------------------------------------------------------

.include 'macros.sp'
.include 'PTM45nm_LP.sp'
.param lambda=24nm vdd=1.0V

.options accurate post
.temp 27

.tran 2ps 4.0ns

.op
.global vdd vcc gnd
.probe

* Power Supplies
Vvdd vdd   gnd dc=vdd
Vvcc vcc   gnd dc=vdd

* Static CMOS Logic Gate
* ----------------------
.subckt xgate1 Ai Bi Ci Di Ei Fo 
Xn0 n0  in0 out nfet
.ends

* Pseudo NMOS Logic Gate
* ----------------------
.subckt xgate2 Ai Bi Ci Di Ei Fo 
.ends

* Dynamic N-Block Logic Gate
* --------------------------
.subckt xgate3 Ai Bi Ci Di Ei Fob Phi
Xbuf Fo Fob inv
.ends

* DCVSL Logic Gate
* ----------------
.subckt xgate4 Ai Bi Ci Di Ei Aib Bib Cib Dib Eib Fo Fob
.ends

* FO4 Power Test
* --------------
Xdrv  Ein Ei   inv
Xdut           xgate
Xld0  out flt0 invT
Xld1  out flt1 invT
Xld2  out flt2 invT
Xld3  out flt3 invT

.end