* EEC 210 Fall 2005 Design Project
* File: 
* Author:  
* Date: 
**
** 
** Design Project: Self-Biased Op Amp with External Compensation
**
**----------------------------------------------------------------------------

.include '130nm_nominal.sp'
.param lambda=65nm vdd=1.2V

.options accurate post
.temp 27

.global vdd gnd
.probe

* Power Supplies
Vvdd vdd   gnd dc=vdd

* Inputs
* add input sources here

* Parameters
* ----------
.param Wmin='5*lambda'

* Three terminal FET macros
* -------------------------
* NOTE: If you use different macros or four terminal FET specifications, you
* must include source/drain area and perimeter parasitics using the same
* calculations as in the following macros.
 
.macro nfet s g d Le='2*lambda' Wi=Wmin
MN0 s g d gnd NMOS L=Le W=Wi AS='5.5*lambda*Wi' PS='2*5.5*lambda+Wi'
+ AD='5.5*lambda*Wi' PD='2*5.5*lambda+Wi'
.eom

.macro pfet s g d Le='2*lambda' Wi=Wmin
MP0 s g d vdd PMOS L=Le W=Wi AS='5.5*lambda*Wi' PS='2*5.5*lambda+Wi'
+ AD='5.5*lambda*Wi' PD='2*5.5*lambda+Wi'
.eom

* Op Amp
* ------
.subckt opamp inp inm out ncmp
* differential self-biased stage
* default sizings - change for your design
Xm1 nbias  inp   ncmp  nfet Le='2*lambda'  Wi='1*Wmin'
Xm2 nbias  inm   gbias nfet Le='2*lambda'  Wi='1*Wmin'
Xm3 ncmp   gbias vdd   pfet Le='2*lambda'  Wi='1*Wmin'
Xm4 gbias  gbias vdd   pfet Le='2*lambda'  Wi='1*Wmin'
Xm5 nbias  gbias gnd   nfet Le='2*lambda'  Wi='1*Wmin'

* output stage 
* specify output stage here
Xm6 
Xm7 
.ends

* Test Circuit and Compensation
* -----------------------------
Xdut inp  inm  out ncmp opamp
Rcmp ncmp cmp0          r=10k
Ccmp out  cmp0          c=10pF

.end