Patrick Satarzadeh
I have joined Texas Instruments
as a part of the Digitally Enhanced Analog
Systems group in the DSP R&D Center
I recently graduated with my Ph.D. in electrical engineering from UC Davis
My general interests lie in implementations of signal processing
systems where in particular I am interested in developing DSP
based methods to calibrate analog/RF circuits.
My advisor was Professor Bernard C. Levy.
My intestest in circuits also allowed me to interact with Professor Paul J. Hurst.
My interest in modeling the HRTF allowed me to work with Professor Ralph V. Algazi.
You can find my old resume here
[pdf].
Research Projects
I have worked on:
- Digital Calibration Methods for Single and Time-Interleaved ADCs
- Novel Equalization Techniques/Architectures for SerDes @ Rambus
- Digitally Controlled Delay Lines (DCDLs) @ Rambus
- Optimization of Pulse Shaping Filters for PA power efficiency@ MIT Lincoln Lab
- Pinna Related Transfer Functions
Papers
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs
Patrick Satarzadeh, Bernard C. Levy, and Paul J. Hurst
submitted to the 2010 IEEE Internat. Symposium on Circuits and Systems (ISCAS '10), Paris, France, May 2010
Digital Calibration of a Nonlinear Sample and Hold (S/H)
Patrick Satarzadeh, Bernard C. Levy, and Paul J. Hurst
IEEE J. Selected Topics in Signal Processing, special issue on DSP
techniques for RF/analog circuits impairments, vol. 3, no. 3, June 2009
. [pdf]
Adaptive Semi-Blind Calibration of a two channel time-interleaved A/D Converter
Patrick Satarzadeh, Bernard C. Levy, and Paul J. Hurst
IEEE Trans. Circuits and Systems I,
vol. 56, pp. 2075--2088, September 2009. [pdf]
Bandwidth Mismatch Correction of a two channel time-interleaved A/D Converter
Patrick Satarzadeh, Bernard C. Levy, and Paul J. Hurst
ISCAS 2007, New Orleans, LA May 2007.
[pdf]
Physical and Filter Pinna Models Based on Anthropometry
Patrick Satarzadeh, Ralph V. Algazi, and Richard O. Duda
122nd Audio Engineering Society(AES) Convention, Vienna, Austria May 2007.
[pdf]
A Study of Physical and Circuit Models of the Human Pinnae
Patrick Satarzadeh, Master's Thesis
[pdf].
Talks
A Recipe for Background ADC Calibration via DSP.
Stanford University, Rethinking Analog Design Initiative, May 2009 (Invited)
A Recipe for Background ADC Calibration via DSP.
Rambus, May 2009 (Invited)
Bandwidth Mismatch Correction of a two channel time-interleaved A/D Converter.
slides
ISCAS, New Orleans, May 2007
Contact Information
Department of Elec/Comp Eng.
One Shields Ave.
Davis, CA 95616
psatarzadeh at ucdavis dot edu