Research

---

Interest

· III-V Semiconductor Nanowire-based Electronic and Photonic Devices: Fabrication and Characterization

· Material Synthesis for Nanowire-based Device Fabrication

· Nanoscale Plasmonic Devices

· Optical Nanofiber for Future Information Highway

· Nutrient Enhancement in Agro-Food Products using Pulse Electric Field (PEF) Treatment

Current Research

Nanoelectronics and NEMs are on the way to dominate future electronic industry. Conventional metal connections in Integrated Circuits (ICs) will be replaced by ultra-thin nanowires allowing exceptionally high speed and high packing density in future ICs. Device dimensions in the range of few nanometers are quite possible and physics of these nanodevices has to be studied in atomic level. Nanocomputing devices and nanobiosensors will play vital role in space and life science research. We have to give birth to nanodevice mass-fabrication techniques that would ultimately lead to commercial realization of nanoelectronic products.

My current research is to investigate heteroepitaxial nanowire growth with highly lattice mismatched materials, and nanowire based electronic and photonic device simulation and fabrication. I am working on the following projects-

A. Nanowire growth using high lattice mismatch materials

For optoelectronic and photonic application direct bandgap materials are the ultimate choice. III-V compound semiconductor and their alloys are very promising for this type of applications. Since III-V semiconductor wafers are considerably costlier than silicon wafers, their large scale commercial use is not feasible. Conceptually it seems plausible that III-V material device layer can be grown on a silicon handle wafer to reduce the cost. However, due to large lattice mismatch and difference in thermal expansion coefficients, growing III-V thin films on silicon is not possible.

Even though growth of III-V thin films on silicon is impossible, researchers have demonstrated that growing nanowire is not difficult when the overlayer and the substrate lattice mismatch is low (e.g. Si/Ge about 4% lattice mismatch). But the growth process is complicated when the lattice mismatch is high (e.g. Si/InP about 8.06%). Difference in thermal expansion coefficients play an important role in releasing the strain energy as the growth is initiated.

Figure 1: Schematic shows III-V nanowire on silicon substrate. When the diameter of the nanowire is within a threshold limit dislocation free coherent nanowire can be grown.

Figure 2: SEM image of metal catalyst assisted CVD grown InP nanowires on SOI substrate. Long tapered nanowires are observed.

Figure 3: SEM image of CVD grown INP nanowires on silicon substrate using gold catalyst. Nanowires are randomly oriented and originate from a root.

B. Precise Positioning or directional growth of nanowire

Random growth of nanowire has been well-demonstrated both in industry and academia. Directional growth of nanowires is very essential for device level applications for using them as interconnect between electrodes or even from one layer to another in a layered fabrication process. INano group has demonstrated a technique for precise positioning of nanowires compatible for massmanufacturing. Figures 4 and 5 demonstrate the technique of metal nanoparticle formation and fabricated metal nanoparticles, respectively.

Figure 4: Metal patterned lines on silicon gradually transform into uniform isolated metal droplets due to Raleigh instability. These metal nanoparticles act as the catalyst for precisely controlled directional growth of nanowires in CVD.

Figure 5: Fabricated metal nanoparticles to be used as catalyst to precisely position nanowires for directional growth.

C. Nanowire based electronic and photonic devices

Our goal is to use nanowires in nanoscale electronics and photonics. This requires the design, fabrication and characterization of individual devices. Once discrete devices can be successfully demonstrated, nanoelectronic systems can be designed. Nanowires are highly promising for photonic application due to their high surface to volume ratio. Nanowire based solar cell units can achieve very high efficiency presumably higher than 50%. Figures 6-8 represent schematics of such single devices.

Figure 6: Nanowire based Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Post growth oxidation followed by metal deposition can be used to realize the device.

Figure 7: High speed InP nanowire based photo detector. This technique can be used to fabricate III-V semiconductor nanowire based high speed photo diode.