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University of California, Davis

M.S. Electrical and Computer Engineering

April 2010

GPA: 3.94

University of California, Davis

B.S. Electrical and Computer Engineering with Honors

June 2004

Emphasis: Digital Circuits and Systems
GPA: 3.53

Software: Cadence Tools, Virtuoso Layout Suite, Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Spectre, SoC Encounter, Synopsys Design Compiler, Sentaurus TCAD, VCS, Aurora, HSPICE, Nanosim, Matlab, Xilinx ISE, Modelsim, Altera Max+Plus II, Mentor Graphics Calibre, SWITCAP, FastCap, Microsoft Office, Visio, Subversion

Operating Systems: Unix, Linux, Microsoft Windows

Laboratory Tools: Oscilloscopes, Logic Analyzers, Power Supplies, Keithley and Tektronix GPIB Interfaces

• Conducted an exploration of pulse width modulation circuitry for on-chip low power interconnect design in a sensor network processing node. Work culminated in a master's thesis and test chip fabricated in 0.25um CMOS technology.
• Participated in the design, simulation, layout, and testing of a fabricated DSP array.
• Modeled and characterized Silicon Nanowire FET devices using TCAD software.
• Created SPICE libraries from Nanowire FET simulations in 90nm and 22nm technologies to evaluate the impact on interconnect and power gating circuitry.
• Created a CAD tool to optimize the design space of a 3D IC reconfigurable architecture.
• Engineered and documented a semi-custom CAD tool flow to test various architectural designs of a low power signal processing array.
• Improved the accuracy of layout parasitic models by editing the DIVA extraction rules.
• Automated testing of custom ICs using C code to interface simultaneously with multiple pieces of lab equipment and check for errors.
• Mentored and familiarized new graduate and undergraduate group members with available systems/software, lab equipment, and ongoing research.

University of California, Davis	Teaching Assistant, ECE Department
Davis, CA	April 2005 - Present

• Led over 20 undergraduate students in weekly lab sections, held office hours, created problem set solutions, and graded assignments in Digital Systems II - 2 quarters, and Digital Integrated Circuits - 1 quarter.
• Debugged SPICE code, lab equipment, and software issues concerning logic synthesis for FPGAs, and digital circuit design.

University of California, Davis	Course Reader, ECE Department
Davis, CA	September 2004 - September 2005

• Evaluated coursework and programs within deadlines for Computer Structure and Assembly Language, Electronic Circuits I, and Circuits I.

University of California, Davis	Student Programmer IV, CS Department
Davis, CA	September 2002 - September 2004

• Maintained, set up, and troubleshot over 100 Red Hat Linux 9.0 and HP-UX computer systems - including network setup/cabling, hardware/software upgrades, and Kickstart installations.
• Provided technical support to students and faculty in person, over the phone, and using an email based tracking system - including account maintenance, login, quota, application, network, and printing problems.
• Developed shell scripts for instructional facility administration.

L. Guo, M. Scott, R. Amirtharajah, "An Energy Scalable Functional Unit for Sensor Signal Processing," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2007, pp. 73-76.

L. Guo, M. Scott, R. Amirtharajah, "An Energy Scalable Computational Array for Sensor Signal Processing," IEEE Custom Integrated Circuits Conference (CICC), 2006, pp. 317-320.